US4011576A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Nonvolatile semiconductor memory devices
Assignee: Toshiba Corp
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Filing: 1975-08-25
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Granted: 1977-03-08
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Expires: 1995-08-25
Abstract
Abstract A nonvolatile semiconductor memory device of the type known as an insulated gate field effect transistor, in which a thick gate insulating layer overlaps the source and drain regions formed in a substrate. The surface of the substrate underlying the thick gate insulating layer is doped lightly with impurities having opposite conductivity relative to the substrate.
Inventors
- 👤 Yukimasa Uchida
- 👤 Takeshi Matsuo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:01
CPC Classifications
H; H10; H10B; H10B41/00; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/605; H10D30/69
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
166 words
A nonvolatile semiconductor memory device comprising: spaced apart source and drain regions of one conductivity type within a semiconductor substrate of the other conductivity type; first and second spaced apart lightly doped regions of the same conductivity type as said source and drain regions, and formed within the semiconductor substrate in between said source and drain regions, said first lightly doped region contacting said source region, and said second lightly doped region contacting said drain region; a first insulating layer formed on the semiconductor substrate, said first insulating layer consisting of a thicker part and a very thin part, said thicker part overlying said source and drain regions and part of said lightly doped regions and said thin part overlying the area between said lightly doped regions and the rest of said lightly doped regions; a second insulating layer applied on said first insulating layer; a gate electrode applied on said second insulating layer; and source and drain electrodes connected to said source and drain regions.
Claim 2
Dependent Claim
166 words
A nonvolatile semiconductor memory device comprising: spaced apart source and drain regions of one conductivity type within a semiconductor substrate of the other conductivity type; first and second spaced apart lightly doped regions of the same conductivity type as said source and drain regions, and formed within the semiconductor substrate in between said source and drain regions, said first lightly doped region contacting said source region, and said second lightly doped region contacting said drain region; a first insulating layer formed on the semiconductor substrate, said first insulating layer consisting of a thicker part and a very thin part, said thicker part overlying said source and drain regions and part of said lightly doped regions and said thin part overlying the area between said lightly doped regions and the rest of said lightly doped regions; a second insulating layer applied on said first insulating layer; a gate electrode applied on said second insulating layer; and source and drain electrodes connected to said source and drain regions.
Claim 3
Dependent Claim
23 words
A nonvolatile semiconductor memory device as in claim 1, wherein: said semiconductor substrate is silicon and said first insulating layer is silicon dioxide.
Claim 4
Dependent Claim
17 words
A nonvolatile semiconductor memory device as in claim 2, wherein: said second insulating layer is silicon nitride.
Claim 5
Dependent Claim
46 words
A nonvolatile semiconductor memory device as in claim 2, wherein: the thickness of said very thin part of said first insulating layer ranges from 10 to 50 angstroms and the thickness of said thicker part of said first insulating layer ranges from 500 to 1500 angstroms.
Claim 6
Dependent Claim
23 words
A nonvolatile semiconductor memory device as in claim 3, wherein: the thickness of said silicon nitride layer ranges from 300 to 1000 angstroms.
Claim 7
Dependent Claim
18 words
A nonvolatile semiconductor memory device as in claim 2, wherein: said semiconductor substrate is n-type (111) oriented silicon.
References Cited (Backward Citations)
US3747203A
Cited
US3845327A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-03-07 | 1980-09-06 | 1981-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-03-07 | 1984-09-06 | 1985-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-03-07 | 1988-09-06 | 1989-03-08 | $7700.00 | Window Closed / Lapsed |