US3845327A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Counter with memory utilizing mnos memory elements
Assignee: Westinghouse Electric Corp
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Filing: 1972-08-16
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Granted: 1974-10-29
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Expires: 1992-08-16
Abstract
Abstract An improved integrated counter stage employing non-volatile MNOS memory elements in series with static load transistors to facilitate a non-complementing counter. Incorporated into the counter are means for reducing memory pulse feedthrough and for providing transient clipping, resulting in increased reliability.
Inventors
- 👤 J Cricchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 12:31
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/69; H03; H03K; H03K21/00; H03K21/40; H03K21/403
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
170 words
IN COMBINATION, A BISTABLE COUNTER STAGE COMPRISING A PAIR OF ELECTRON VALVES INTERCONNECTED SUCH THAT WHEN ONE VALVE CONDUCTS THE OTHER IS CUT OFF AND VICE VERSA, A METALNITRIDE-OXIDE SEMICONDUCTOR MEMORY DEVICE AND A LOAD ELEMENT CONNECTED IN SERIES WITH EACH OF SAID VALVES SUCH THAT CURRENT CAN FLOW THROUGH A VALVE AND THENCE BETWEEN THE SOURCE AND DRAIN OF A MEMORY ELEMENT TO SAID LOAD ELEMENT, EACH OF SAID MEMORY ELEMENTS BEING CAPABLE OF STORING AT A NITRIDE-OXIDE INTERFACE ELECTRONIC STATES REPRESENTATIVE OF A CONDUCTING OR NON-CONDUCTING CONDITION OF ITS ASSOCIATED ELECTRON VALVE, MEANS FOR APPLYING A PULSE TO THE GATE ELECTRODES OF SAID MEMORY DEVICES AFTER EACH CHANGE OF STATE OF SAID BISTABLE STAGE TO CLEAR THE PREVIOUSLY STORED ELECTRONIC STATES AT THE NITRIDE-OXIDE INTERFACES OF THE RESPECTIVE MEMORY DEVICES, AND MEANS FOR PREVENTING FEEDTHROUGH OF SAID PULSE TO SAID BISTABLE STAGE, SAID LAST-MENTIONED MEANS INCLUDING A REGION OF REDUCED THICKNESS IN A SILICON DIOXIDE LAYER BETWEEN THE SOURCE AND DRAIN REGIONS OF EACH OF THE MEMORY ELEMENTS.
Claim 2
Dependent Claim
170 words
IN COMBINATION, A BISTABLE COUNTER STAGE COMPRISING A PAIR OF ELECTRON VALVES INTERCONNECTED SUCH THAT WHEN ONE VALVE CONDUCTS THE OTHER IS CUT OFF AND VICE VERSA, A METALNITRIDE-OXIDE SEMICONDUCTOR MEMORY DEVICE AND A LOAD ELEMENT CONNECTED IN SERIES WITH EACH OF SAID VALVES SUCH THAT CURRENT CAN FLOW THROUGH A VALVE AND THENCE BETWEEN THE SOURCE AND DRAIN OF A MEMORY ELEMENT TO SAID LOAD ELEMENT, EACH OF SAID MEMORY ELEMENTS BEING CAPABLE OF STORING AT A NITRIDE-OXIDE INTERFACE ELECTRONIC STATES REPRESENTATIVE OF A CONDUCTING OR NON-CONDUCTING CONDITION OF ITS ASSOCIATED ELECTRON VALVE, MEANS FOR APPLYING A PULSE TO THE GATE ELECTRODES OF SAID MEMORY DEVICES AFTER EACH CHANGE OF STATE OF SAID BISTABLE STAGE TO CLEAR THE PREVIOUSLY STORED ELECTRONIC STATES AT THE NITRIDE-OXIDE INTERFACES OF THE RESPECTIVE MEMORY DEVICES, AND MEANS FOR PREVENTING FEEDTHROUGH OF SAID PULSE TO SAID BISTABLE STAGE, SAID LAST-MENTIONED MEANS INCLUDING A REGION OF REDUCED THICKNESS IN A SILICON DIOXIDE LAYER BETWEEN THE SOURCE AND DRAIN REGIONS OF EACH OF THE MEMORY ELEMENTS.
Claim 3
Dependent Claim
65 words
The combination of claim 1 wherein the source and drain regions of each memory element are formed in a semiconducting substrate, the layer of silicon dioxide being formed over said substrate above said source and drain regions, and a layer of silicon nitride covering said layer of silicon dioxide, said electronic states being formed at the interface between said silicon nitride and silicon dioxide layers.
Claim 4
Dependent Claim
62 words
The combination of claim 2 wherein the thickness of the silicon dioxide layer on opposite sides of said region of reduced thickness upon application of said pulse is such as to reduce the field in the oxide between the gate and source rEgions to such a value that a change of state of said counter due to current feedthrough does not occur.
Claim 5
Dependent Claim
27 words
The combination of claim 1 wherein said electron valves and said load elements also comprise metal-nitride-oxide semiconductor devices formed on a single substrate with said memory devices.
Claim 6
Dependent Claim
88 words
The combination of claim 1 including metal-nitride-oxide semiconductor keeper elements for each of said memory elements, said keeper elements being connected with their source and drain elements in parallel with the parallel combination of a memory element and a load element, means for applying a potential negative relative to the potential on the source to the drain element of each of said keeper elements, and means for applying a potential negative relative to the potential on the source to the gate electrodes of each of said keeper elements.
Claim 7
Dependent Claim
40 words
The combination of claim 5 including metal-nitride-oxide semiconductor devices for applying pulses to be counted to the electron valves of said bistable stage, and means for deriving from said stage a single output pulse for every two input pulses counted.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-28 | 1978-04-29 | 1978-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-28 | 1982-04-29 | 1982-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-28 | 1986-04-29 | 1986-10-29 | $7700.00 | Window Closed / Lapsed |