← Back to Patent Explorer
US5272097A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for fabricating diodes for electrostatic discharge protection and voltage references

Assignee: Individual
•
Filing: 1992-04-07
•
Granted: 1993-12-21
•
Expires: 2012-04-07
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A novel process is taught for forming diodes simultaneously with the formation of typical prior art LDD MOS devices. The diodes thus formed have low breakdown voltages, making them suitable for use as voltage reference diodes, or diodes for ESD protection.

Inventors

  • 👤 Philip Shiota

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 20:41
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/811; H10D89/00; H10D89/60; H10D89/601; H10D89/611; H10D89/711

Claims Analysis

Total Claims: 20
Claim 1
Independent Claim 331 words
A method of fabricating a semiconductor structure comprising the steps of: a) forming within a first bulk region (1103) of a first conductivity type, a lightly doped source/drain region (1111) of a second conductivity type opposite said first conductivity type; b) forming within a second bulk region (1102) of said second conductivity type, a second conductivity type lightly doped portion (1110) of a first diode region; c) forming within said second bulk region (1102) a lightly doped source/drain region (1120) of said first conductivity type; d) forming within said first bulk region (1103) a first conductivity type lightly doped portion (1121) of a first diode region; e) forming within said first bulk region (1103) a second conductivity type portion (1114) of said first diode region; f) forming within said first bulk region (1103) a source/drain region (1115) of said second conductivity type; g) forming within said second bulk region (1102) a second diode region (1116) of said second conductivity type; h) forming within said first bulk region (1103) a second diode region (1119) of said first conductivity type; i) forming within said second bulk region (1102) a source/drain region (1118) of said first conductivity type; and j) forming within said second bulk region (1102) a first conductivity type portion (1117) of said first diode region, wherein said first bulk region comprises a lightly doped source/drain MOS device and a diode having said second conductivity type portion of said first diode region formed within said first bulk region serving as a first terminal of said diode and said second diode region within said first bulk region serves as a second terminal of said diode, and wherein said second bulk region comprises a lightly doped source/drain MOS device and a diode having said first conductivity type portion of said first diode region within said second bulk region serving as a first terminal of said diode and said second diode region within said second bulk region serves as a second terminal of said diode.
Claim 2
Independent Claim 331 words
A method of fabricating a semiconductor structure comprising the steps of: a) forming within a first bulk region (1103) of a first conductivity type, a lightly doped source/drain region (1111) of a second conductivity type opposite said first conductivity type; b) forming within a second bulk region (1102) of said second conductivity type, a second conductivity type lightly doped portion (1110) of a first diode region; c) forming within said second bulk region (1102) a lightly doped source/drain region (1120) of said first conductivity type; d) forming within said first bulk region (1103) a first conductivity type lightly doped portion (1121) of a first diode region; e) forming within said first bulk region (1103) a second conductivity type portion (1114) of said first diode region; f) forming within said first bulk region (1103) a source/drain region (1115) of said second conductivity type; g) forming within said second bulk region (1102) a second diode region (1116) of said second conductivity type; h) forming within said first bulk region (1103) a second diode region (1119) of said first conductivity type; i) forming within said second bulk region (1102) a source/drain region (1118) of said first conductivity type; and j) forming within said second bulk region (1102) a first conductivity type portion (1117) of said first diode region, wherein said first bulk region comprises a lightly doped source/drain MOS device and a diode having said second conductivity type portion of said first diode region formed within said first bulk region serving as a first terminal of said diode and said second diode region within said first bulk region serves as a second terminal of said diode, and wherein said second bulk region comprises a lightly doped source/drain MOS device and a diode having said first conductivity type portion of said first diode region within said second bulk region serving as a first terminal of said diode and said second diode region within said second bulk region serves as a second terminal of said diode.
Claim 3
Dependent Claim 14 words
A method as in claim 1, wherein steps a and b are performed simultaneously.
Claim 4
Dependent Claim 18 words
A method as in claim 2, wherein steps a and b are performed simultaneously using a blanket implant.
Claim 5
Dependent Claim 14 words
A method as in claim 1, wherein steps c and d are performed simultaneously.
Claim 6
Dependent Claim 15 words
A method as in claim 1, wherein steps e, f, and g are performed simultaneously.
Claim 7
Dependent Claim 15 words
A method as in claim 1, wherein steps h, i, and j are performed simultaneously.
Claim 8
Dependent Claim 75 words
A method as in claim 1, wherein one or both of said steps of forming within said bulk region said lightly doped source/drain regions utilizes gate electrodes as a portion of a mask and wherein said steps of forming within said bulk regions said source/drain regions utilize gate electrode sidewall spacers as a portion of a mask, thereby providing said source/drain regions laterally spaced apart from said gate electrode by a lightly doped source/drain region.
Claim 9
Dependent Claim 24 words
A method as in claim 3, wherein regions implanted by said blanket implant are over compensated in subsequent doping steps of opposite conductivity type.
Claim 10
Independent Claim 207 words
A method of fabricating a semiconductor structure comprising the steps of: a) forming within a first bulk region (5103) of a first conductivity type, a lightly doped source/drain region (5111) of a second conductivity type opposite said first conductivity type; b) forming within one or more second bulk regions (5102) of said second conductivity type, a second conductivity type lightly doped portion (5110) of a first diode region; c) forming within said first bulk region (5103) a source/drain region (5115) of said second conductivity type; d) forming within said second bulk regions (5102) a second diode region (5116) of said second conductivity type; e) forming within said second bulk regions (5102) a source/drain region (5118) of said first conductivity type; and f) forming within said second bulk regions (5102) a first conductivity type portion (5117) of said first diode region, wherein said first bulk regions comprise a lightly doped source/drain MOS device, and wherein said second bulk regions comprise a MOS device and a diode having said first conductivity type portion of said first diode region within said second bulk regions serving as a first terminal of said diode and said second diode region within said second bulk regions serve as a second terminal of said diode.
Claim 11
Independent Claim 207 words
A method of fabricating a semiconductor structure comprising the steps of: a) forming within a first bulk region (5103) of a first conductivity type, a lightly doped source/drain region (5111) of a second conductivity type opposite said first conductivity type; b) forming within one or more second bulk regions (5102) of said second conductivity type, a second conductivity type lightly doped portion (5110) of a first diode region; c) forming within said first bulk region (5103) a source/drain region (5115) of said second conductivity type; d) forming within said second bulk regions (5102) a second diode region (5116) of said second conductivity type; e) forming within said second bulk regions (5102) a source/drain region (5118) of said first conductivity type; and f) forming within said second bulk regions (5102) a first conductivity type portion (5117) of said first diode region, wherein said first bulk regions comprise a lightly doped source/drain MOS device, and wherein said second bulk regions comprise a MOS device and a diode having said first conductivity type portion of said first diode region within said second bulk regions serving as a first terminal of said diode and said second diode region within said second bulk regions serve as a second terminal of said diode.
Claim 12
Dependent Claim 14 words
A method as in claim 9, wherein steps a and b are performed simultaneously.
Claim 13
Dependent Claim 18 words
A method as in claim 10, wherein steps a and b are performed simultaneously using a blanket implant.
Claim 14
Dependent Claim 14 words
A method as in claim 9, wherein steps c and d are performed simultaneously.
Claim 15
Dependent Claim 13 words
A method as in claim 9, wherein steps e and f are simultaneously.
Claim 16
Dependent Claim 28 words
A method as in claim 9, which further comprises the s of forming within said second bulk regions (5102) a doped source/drain region of said first conductivity type.
Claim 17
Dependent Claim 75 words
A method as in claim 14, wherein one or both of said steps of forming within said bulk regions said lightly doped source/drain regions utilizes gate electrodes as a portion of a mask and wherein said steps of forming within said bulk regions said source/drain regions utilize gate electrode sidewall spacers as a portion of a mask, thereby providing said source/drain regions laterally spaced apart from said gate electrode by a lightly doped source/drain region.
Claim 18
Dependent Claim 24 words
A method as in claim 11, wherein regions implanted by said blanket implant are over compensated in subsequent doping steps of opposite conductivity type.
Claim 19
Dependent Claim 25 words
A method as in claim 9 which further comprises the step of forming within said first bulk region (5103) a first conductivity type well contact.
Claim 20
Dependent Claim 32 words
A method as in claim 17 wherein said step of forming said first conductivity well contact is performed simultaneously with said step of forming said source/drain region within said second bulk regions.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-12-20 1997-06-21 1997-12-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-12-20 2001-06-21 2001-12-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-12-20 2005-06-21 2005-12-21 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag