US5144518A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1990-06-26
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Granted: 1992-09-01
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Expires: 2010-06-26
Abstract
Abstract A semiconductor integrated circuit according to the present invention has a series circuit of a first field effect transistor and a load which is connected between a first potential point and a second potential point. The first field effect transistor operates in response to a control signal inputted in a gate thereof, whereby a high-level or low-level output signal is extracted from a node between the first field effect transistor and the load to output terminal. A second field effect transistor is also connected between the output terminal and the first potential point. Thus, when a surge causing the first field effect transistor to break down is applied to the output terminal, the second field effect transistor conducts to pass a surge current, whereby the first field effect transistor is prevented from being broken down.
Inventors
- 👤 Yukio Miyazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:32
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H03; H03K; H03K17/00; H03K17/08; H03K17/081; H03K17/0814; H03K17/08142; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/0165; H10D84/0167; H10D84/80; H10D84/811; H10D84/817
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
130 words
A semiconductor integrated circuit for improving a withstand surge voltage of an output circuit formed by high breakdown voltage field effect transistors, comprising: an input terminal for receiving a control signal; a first field effect transistor having a first electrode and a bulk connected to a first potential point, a control electrode connected to said input terminal and a second electrode; a load connected between said second electrode of said first field effect transistor and a second potential point; an output terminal connected to said second electrode of said first field effect transistor; and a second field effect transistor having a first electrode and a control electrode connected to said output terminal, a second electrode connected to said second potential point and a bulk connected to said first potential point.
Claim 2
Dependent Claim
130 words
A semiconductor integrated circuit for improving a withstand surge voltage of an output circuit formed by high breakdown voltage field effect transistors, comprising: an input terminal for receiving a control signal; a first field effect transistor having a first electrode and a bulk connected to a first potential point, a control electrode connected to said input terminal and a second electrode; a load connected between said second electrode of said first field effect transistor and a second potential point; an output terminal connected to said second electrode of said first field effect transistor; and a second field effect transistor having a first electrode and a control electrode connected to said output terminal, a second electrode connected to said second potential point and a bulk connected to said first potential point.
Claim 3
Dependent Claim
42 words
A semiconductor integrated circuit in accordance with claim 1, wherein said first and second field effect transistors are p-channel MOS transistors respectively, and said first potential point is a high potential point while said second potential point is a low potential point.
Claim 4
Dependent Claim
42 words
A semiconductor integrated circuit in accordance with claim 1, wherein said first and second field effect transistors are n-channel MOS transistors respectively, and said first potential point is a low potential point while said second potential point is a high potential point.
Claim 5
Dependent Claim
34 words
A semiconductor integrated circuit in accordance with claim 1, wherein said first and second field effect transistors are high breakdown voltage transistors each of which has a source and a drain of double diffusion.
Claim 6
Dependent Claim
38 words
A semiconductor integrated circuit in accordance with either of claims 2 or 3, wherein said first and second field effect transistors are high breakdown voltage transistors each of which has a source and a drain of double diffusion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-01 | 1996-03-02 | 1996-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-01 | 2000-03-02 | 2000-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-01 | 2004-03-02 | 2004-09-01 | $7700.00 | Window Closed / Lapsed |