Semiconductor device having protective element

Claim 1

A semiconductor device having a protective transistor for protecting an internal circuit from an excess voltage applied to an input terminal, said transistor comprising: a source region formed in a major surface of a semiconductor substrate of a first conductivity type and having a second conductivity type opposite to said first conductivity type, said source region being connected to an earth potential line; a drain region formed in said major surface of said semiconductor substrate and having said second conductivity type, said drain region being connected to said input terminal through a protective resistor element; a first channel region abutted against said source region and having a value of a threshold voltage; a second channel region provided between said first channel region and said drain region and abutted against said first channel region and against said drain region, said second channel region having a channel length between said first channel region and said drain region; a thick insulating layer formed on said first channel region, said thick insulating layer having a bottom depressed from said major surface in which said source and drain regions are formed such that said first channel region under said bottom is depressed from said major surface, a first side wall facing said source region and a second side wall facing said second channel region; an insulating film having a thickness less than that of said thick insulating layer and formed on said second channel region; an impurity region of said second conductivity type having an island-like configuration and formed in said substrate of said first conductivity type; a polycrystalline silicon electrode formed on said insulating film above said second channel region, said silicon electrode being connected to said impurity region so as to connect said silicon electrode to said substrate through an PN junction between said impurity region and said substrate and to maintain said silicon electrode in a floating state; an inter-ply insulating layer covering said silicon electrode above said second channel region and covering said thick insulating layer above said first channel region; and a gate electrode connected to said input terminal and formed on said inter-ply insulating layer above said first and second channel region, said channel length of said second channel region being such that when an abnormal excess voltage at a level equal to or more than said value of said threshold voltage of said first channel region is through said input terminal, a depletion layer from said drain region reaches to said second side wall of said thick insulating layer facing said second channel region, and when a normal operation voltage is applied to said gate electrode, a depletion layer from said drain region is absent at said second side wall.