Staged CMOS output buffer

Claim 2

An output buffer, comprising: a resistor-capacitor (RC) delay circuit having an output and having an input coupled to an input node of said output buffer; a first driver stage having (i) first and second inputs coupled to said input node, (ii) an output coupled to an output node of said output buffer, (iii) a driver having a pull-up transistor and a pull-down transistor coupled to said output, and (iv) a predriver coupled to said driver having means for turning on an inactive one of said driver transistors from said first input and means for turning off the other one of said driver transistors from said second input; and a second driver stage having (i) first and second inputs, said first input coupled to said output of said RC delay circuit, and said second input coupled to said input node, (ii) an output coupled to said output node of said output buffer, (iii) a driver having a pull-up transistor and a pull-down transistor coupled to said output, and (iv) a predriver coupled to said driver having means for turning on an inactive one of said driver transistors from said first input and means for turning off the other one of said driver transistors from said second input.

Claim 3

An output buffer according to claim 1, wherein said RC delay circuit comprises: a substantially square PMOS transistor whose gate is connected to the output of said RC delay circuit and whose source/drains are connected to a first reference node; and a substantially square NMOS transistor whose gate is connected to the output of said RC delay circuit and whose source/drains are connected to a second reference node.

Claim 4

An output buffer according to claim 2, wherein said first and second reference nodes are electrically isolated and have different DC voltages.

Claim 5

An output buffer according to claim 3, wherein said first reference node is a positive voltage source and said second reference node is ground.

Claim 6

An output buffer according to claim 1, wherein said predriver comprises: high and low enable inputs to respectively receive high and low versions of a tri-state enable signal to be supplied to said output buffer; a first pass chain having two PMOS pass transistors connected in series between said first input and the gate of said pull-up transistor in said driver and whose gates are respectively coupled to said second input and to said low enable input; two NMOS pull-down transistors connected to the driver side of said first pass chain and whose gates are respectively coupled to said second input and to said low enable input; a second pass chain having two NMOS pass transistors connected in series between said first input and the gate of said pull-down transistor in said driver and whose gates are respectively coupled to said second input and to said high enable input; and two PMOS pull-up transistors connected to the driver side of said second pass chain and whose gates are respectively coupled to said second input and to said high enable input.

Claim 7

An output buffer according to claim 5, further comprising: a first inverter connected between said first input and said pass chains; a second inverter connected between said first pass chain and the gate of said pull-up transistor in said driver; and a third inverter connected between said second pass chain and the gate of said pull-down transistor in said driver.

Claim 8

An output buffer according to claim 1, further comprising: a number of additional RC delay circuits coupled in series with said RC delay circuit; and the same number of additional driver stages each substantially identical to said first and second stages and having its output coupled to said output node, its first input coupled to the output of a corresponding one of said additional RC delay circuits, and its second input coupled to said input node.

Claim 9

An output buffer according to claim 1, wherein said pull-up transistor in said first stage is the same size as said pull-up transistor in said second stage, and wherein said pull-down transistor in said first stage is the same size as said pull-down transistor in said second stage.

Claim 10

An output buffer according to claim 1, wherein each of said driver stages further comprises: a first termination resistor connected between said pull-up transistor and said output node; and a second termination resistor connected between said pull-down transistor and said output node.

Claim 11

An output buffer according to claim 9, wherein the resistances of said termination resistors are substantially equal.

Claim 12

An output buffer according to claim 1, wherein each of said driver stages further comprises means for tri-stating the output of said driver.

Claim 13

An output buffer, comprising: a delay resistor having one terminal coupled to an input node of said output buffer; a substantially square PMOS transistor whose gate is connected to the other terminal of said delay resistor and whose source/drains are connected to a positive voltage source; a substantially square NMOS transistor whose gate is connected to the other terminal of said delay resistor and whose source/drains are connected to ground; a first driver stage having (i) first and second inputs connected to said one terminal of said delay resistor, (ii) high and low enable inputs to respectively receive high and low versions of a tri-state enable signal to be supplied to said output buffer, (iii) an output connected to an output node of said output buffer, (iv) an output PMOS pull-up transistor, (v) an output NMOS pull-down transistor, (vi) a first termination resistor connected between said output PMOS pull-up transistor and said output, (vii) a second termination resistor having resistance substantially equal to that of said first termination resistor and connected between said output NMOS pull-down transistor and said output, (viii) a first inverter whose input is connected to said first input, (ix) a first pass chain connected at one end to the output of said first inverter and having two PMOS pass transistors connected in series whose gates are respectively connected to said second input and to said low enable input, (x) two NMOS pull-down transistors connected to the other end of said first pass chain and whose gates are respectively connected to said second input and to said low enable input, (xi) a second pass chain connected at one end to the output of said first inverter and having two NMOS pass transistors connected in series whose gates are respectively connected to said second input and to said high enable input, (xii) two PMOS pull-up transistors connected to the other end of said second pass chain and whose gates are respectively connected to said second input and to said high enable input, (xiii) a second inverter connected between the other end of said first pass chain and the gate of said output PMOS pull-up transistor, and (xiv) a third inverter connected between the other end of said second pass chain and the gate of said output NMOS pull-down transistor; and a second driver stage having (i) first and second inputs, said first input connected to the other terminal of said delay resistor, and said second input connected to said one terminal of said delay resistor, (ii) high and low enable inputs to respectively receive said high and low versions of said tri-state enable signal, (iii) an output connected to said output node of said output buffer, (iv) an output PMOS pull-up transistor, (v) an output NMOS pull-down transistor, (vi) a first termination resistor connected between said output PMOS pull-up transistor and said output, (vii) a second termination resistor having resistance substantially equal to that of said first termination resistor and connected between said output NMOS pull-down transistor and said output, (viii) a first inverter whose input is connected to said first input, (ix) a first pass chain connected at one end to the output of said first inverter and having two PMOS pass transistors connected in series whose gates are respectively connected to said second input and to said low enable input, (x) two NMOS pull-down transistors connected to the other end of said first pass chain and whose gates are respectively connected to said second input and to said low enable input, (xi) a second pass chain connected at one end to the output of said first inverter and having two NMOS pass transistors connected in series whose gates are respectively connected to said second input and to said high enable input, (xii) two PMOS pull-up transistors connected to the other end of said second pass chain and whose gates are respectively connected to said second input and to said high enable input, (xiii) a second inverter connected between the other end of said first pass chain and the gate of said output PMOS pull-up transistor, and (xiv) a third inverter connected between the other end of said second pass chain and the gate of said output NMOS pull-down transistor.

Claim 14

An output buffer, comprising: a delay resistor having one terminal coupled to an input node of said output buffer; a substantially square PMOS transistor whose gate is connected to the other terminal of said delay resistor and whose source/drains are connected to a positive voltage source; a substantially square NMOS transistor whose gate is connected to the other terminal of said delay resistor and whose source/drains are connected to ground; a first driver stage having (i) first and second inputs connected to said one terminal of said delay resistor, (ii) high and low enable inputs to respectively receive high and low versions of a tri-state enable signal to be supplied to said output buffer, (iii) an output connected to an output node of said output buffer, (iv) an output PMOS pull-up transistor, (v) an output NMOS pull-down transistor, (vi) a first termination resistor connected between said output PMOS pull-up transistor and said output, (vii) a second termination resistor having resistance substantially equal to that of said first termination resistor and connected between said output NMOS pull-down transistor and said output, (viii) a first inverter whose input is connected to said first input, (ix) a first pass chain connected at one end to the output of said first inverter and having two PMOS pass transistors connected in series whose gates are respectively connected to said second input and to said low enable input, (x) two NMOS pull-down transistors connected to the other end of said first pass chain and whose gates are respectively connected to said second input and to said low enable input, (xi) a second pass chain connected at one end to the output of said first inverter and having two NMOS pass transistors connected in series whose gates are respectively connected to said second input and to said high enable input, (xii) two PMOS pull-up transistors connected to the other end of said second pass chain and whose gates are respectively connected to said second input and to said high enable input, (xiii) a second inverter connected between the other end of said first pass chain and the gate of said output PMOS pull-up transistor, and (xiv) a third inverter connected between the other end of said second pass chain and the gate of said output NMOS pull-down transistor; and a second driver stage having (i) first and second inputs, said first input connected to the other terminal of said delay resistor, and said second input connected to said one terminal of said delay resistor, (ii) high and low enable inputs to respectively receive said high and low versions of said tri-state enable signal, (iii) an output connected to said output node of said output buffer, (iv) an output PMOS pull-up transistor, (v) an output NMOS pull-down transistor, (vi) a first termination resistor connected between said output PMOS pull-up transistor and said output, (vii) a second termination resistor having resistance substantially equal to that of said first termination resistor and connected between said output NMOS pull-down transistor and said output, (viii) a first inverter whose input is connected to said first input, (ix) a first pass chain connected at one end to the output of said first inverter and having two PMOS pass transistors connected in series whose gates are respectively connected to said second input and to said low enable input, (x) two NMOS pull-down transistors connected to the other end of said first pass chain and whose gates are respectively connected to said second input and to said low enable input, (xi) a second pass chain connected at one end to the output of said first inverter and having two NMOS pass transistors connected in series whose gates are respectively connected to said second input and to said high enable input, (xii) two PMOS pull-up transistors connected to the other end of said second pass chain and whose gates are respectively connected to said second input and to said high enable input, (xiii) a second inverter connected between the other end of said first pass chain and the gate of said output PMOS pull-up transistor, and (xiv) a third inverter connected between the other end of said second pass chain and the gate of said output NMOS pull-down transistor.