Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
161 words
A circuit for generating two control signals in response to an input signal, said circuit comprising: a pull up transistor having a first and a second terminal and a gate; a passing gate comprising an N-channel transistor and a p-channel transistor, where the N-channel transistor and the P-channel transistor define two channels; and a pull down transistor having a first and a second terminal and a gate, where the pull-up transistor and the pull-down transistor define two transistors, the first terminals of the two transistors being connected through said passing gate, said gates of the two transistors being controlled by the input signal, wherein a first control signal at the second terminal of the pull up transistor has a fast rise time and slow fall time with respect to the input signal and a second control signal at the second terminal of the pull down transistor has a fast fall time and slow rise time with respect to the input signal.
Claim 2
Dependent Claim
161 words
A circuit for generating two control signals in response to an input signal, said circuit comprising: a pull up transistor having a first and a second terminal and a gate; a passing gate comprising an N-channel transistor and a p-channel transistor, where the N-channel transistor and the P-channel transistor define two channels; and a pull down transistor having a first and a second terminal and a gate, where the pull-up transistor and the pull-down transistor define two transistors, the first terminals of the two transistors being connected through said passing gate, said gates of the two transistors being controlled by the input signal, wherein a first control signal at the second terminal of the pull up transistor has a fast rise time and slow fall time with respect to the input signal and a second control signal at the second terminal of the pull down transistor has a fast fall time and slow rise time with respect to the input signal.
Claim 3
Dependent Claim
46 words
The circuit of claim 1, wherein said passing gate includes two gates, each of the two gates controlling one of the two channels, said circuit further comprising enabling means for controlling the two gates of the passing gate for turning the passing gate on or off.
Claim 4
Dependent Claim
102 words
The circuit of claim 2, wherein said circuit is implemented in an integrated circuit chip having an output pin, and wherein said two control signals are suitable for controlling a buffer, said buffer having an output so that when the enabling means enables the passing gate, the buffer passes the input signal to the output of the buffer at an output pin, and wherein said enabling means includes means for disabling the buffer while the passing gate is turned off so that said buffer is electrically isolated from the output pin so that the output pin is usable as an input pin.
Claim 5
Dependent Claim
23 words
The circuit of claim 1, wherein the pull up transistor is a p-channel FET and the pull down transistor is an n-channel FET.
Claim 6
Dependent Claim
178 words
A precharge circuit for controlling a static random access memory, said memory including memory cells, where a given memory cell is connected to at least one bit line for supplying data to the memory cell and to a select line for selecting the memory cell to which the data on the bit line is to be written, said circuit comprising: a pull up transistor having a first and a second terminal and a gate; a passing gate comprising an N-channel transistor and a P-channel transistor, where the N-channel transistor and P-transistor define two channels, and where both channels are fixed open; a pull down transistor having a first and a second terminal and a gate, where the pull up and pull down transistors define two transistors, the second terminals of the two transistors being connected through said passing gate, said gates of the two transistors being controlled by a single signal or signals derived therefrom; means for applying voltages to the first terminals of the two transistors or signals derived therefrom to control the bit and select lines.
Claim 7
Dependent Claim
178 words
A precharge circuit for controlling a static random access memory, said memory including memory cells, where a given memory cell is connected to at least one bit line for supplying data to the memory cell and to a select line for selecting the memory cell to which the data on the bit line is to be written, said circuit comprising: a pull up transistor having a first and a second terminal and a gate; a passing gate comprising an N-channel transistor and a P-channel transistor, where the N-channel transistor and P-transistor define two channels, and where both channels are fixed open; a pull down transistor having a first and a second terminal and a gate, where the pull up and pull down transistors define two transistors, the second terminals of the two transistors being connected through said passing gate, said gates of the two transistors being controlled by a single signal or signals derived therefrom; means for applying voltages to the first terminals of the two transistors or signals derived therefrom to control the bit and select lines.
Claim 8
Dependent Claim
23 words
The circuit of claim 5, wherein the pull up transistor is a p-channel FET and the pull down transistor is an n-channel FET.
Claim 9
Dependent Claim
43 words
The circuit of claim 5, wherein the signal at the second terminal of the pull up transistor is applied to control the bit line and the signal at the second terminal of the pull down transistor is applied to control the select line.