Precharge circuit for use in a semiconductor memory device

Claim 1

A precharge circuit for a static random access memory including a pair of bit lines (BL, BL), a plurality of memory cells coupled between the bit line pair, a first means coupled between the power supply source and respective one of the bit line pair for precharging the bit line pair in response to a first clock pulse (φWE) provided by a write enable pulse in a precharge cycle performed prior to a read operation, a second means (11, 12, 13) coupled between the bit line pair for precharging and equalizing the bit line pair in response to a second clock pulse (EQ) provided by an address transition detection pulse in the precharge cycle, a pair of diode-connected transistor means coupled between the power supply source and respective ones of the bit line pair and normally turned on, characterized in that said first precharging means comprises a pair of N-channel MOS transistors (16, 17) whose gates are coupled to the first clock pulse and whose drain-source paths are coupled between the power supply source and respective ones of the bit line pair, wherein said transistor pair precharge the bit line pair to a predtermined potential value in response to said first clock pulse in the precharge cycle performed prior to a read operation and thereafter said second precharging and equalizing means successively precharges the bit line pair in response to the second clock pulse more dominantly than said transistor pair.