Gate output driver using slew-rate control

Claim 1

A circuit for controlling the output of an integrated circuit to limit the rate of change of output current comprising: an output inverter having a P-channel output transistor having a P-gate and being connected between a positive power supply terminal and an output node and an N-channel output transistor having an N-gate and being connected between said output node and a negative power supply terminal; a first bias circuit connected to said P-gate and comprising a first P-channel bias transistor connected to said positive power supply terminal, a first N-channel bias transistor that is connected between said P-channel bias transistor and said first P-gate and a second N-channel bias transistor connected between said P-gate and said negative power supply terminal; a second bias circuit connected to said N-gate and comprising a second P-channel bias transistor connected to said N-gate, a third N-channel bias transistor connected between said second P-channel bias transistor and said negative power supply terminal, and a third P-channel bias transistor connected between said N-gate and said positive power supply terminal, in which; said output node is connected to a gate of said first P-channel bias transistor and to a gate of said third N-channel bias transistor; and said first and second N-channel bias transistors, and said second and third P-channel bias transistors are all controlled by an input node that is also connected to said P-gate and said N-gate.