US4634893A
Expired / Lapsed
US
⏱️ 0.0 years remaining
FET driver circuit with mask programmable transition rates
Assignee: MagnaChip Semiconductor Ltd
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Filing: 1985-02-25
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Granted: 1987-01-06
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Expires: 2005-02-25
Abstract
Abstract A field effect transistor driver circuit figured to have different rates of change of the output signal depending on fabrication mask designation of selected transistors to be either depletion or enhancement type devices.
Inventors
- 👤 Donald G. Craycraft
- 👤 Giao N. Pham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:48
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/14; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C17/123; G11C7/06; G11C7/062; G11C7/18
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
97 words
An integrated driver circuit for programmably prescribing the rate of change of the output signal, comprising: an amplifier having series connected, push-pull connected output FETs responsive respectively to oppositely transitioned potentials on first and second capacitively acting nodes; means for selectively limiting the rate of change of the potential on the first capacitive node by providing current to charge said first capacitive node at a programmed rate; and means for selectively limiting the rate of change of the potential on the second capacitive node by providing current to charge said second capacitive node at a programmed rate.
Claim 2
Dependent Claim
97 words
An integrated driver circuit for programmably prescribing the rate of change of the output signal, comprising: an amplifier having series connected, push-pull connected output FETs responsive respectively to oppositely transitioned potentials on first and second capacitively acting nodes; means for selectively limiting the rate of change of the potential on the first capacitive node by providing current to charge said first capacitive node at a programmed rate; and means for selectively limiting the rate of change of the potential on the second capacitive node by providing current to charge said second capacitive node at a programmed rate.
Claim 3
Dependent Claim
60 words
The driver circuit recited in claim 1, wherein said means for providing current to each capacitive node comprises: a current limiting resistive element; and a pass FET which is programmed in either a depletion or enhancement mode, connected in conductive series between said resistor element and the respective capacitive node, and having its gate electrode biased at a fixed potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-05 | 1990-07-07 | 1991-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-05 | 1994-07-07 | 1995-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-05 | 1998-07-07 | 1999-01-06 | $7700.00 | Window Closed / Lapsed |