US4103189A
Expired / Lapsed
US
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Mos buffer circuit
Assignee: Intel Corp
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Filing: 1977-07-25
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Granted: 1978-07-25
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Expires: 1997-07-25
Abstract
Abstract An MOS buffer circuit which may be employed as part of a electrically programmable read-only memory or other MOS integrated circuit is described. The buffer may be "powered down" when the memory is in a standby mode. Low threshold (zero threshold) voltage devices are employed in the circuit along with depletion mode transistors and enhancement mode transistors in a manner which permits the buffer to be readily powered down.
Inventors
- 👤 George Perlegos
- 👤 Phillip J. Salsbury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 04:20
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/08; G11C16/10; G11C16/12; G11C16/20
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
148 words
A stage for a metal-oxide-semiconductor (MOS) buffer comprising: an enhancement mode, field-effect transistor having a gate coupled to receive an input signal for said stage; a load coupled in series with said enhancement mode transistor for providing an output signal from said stage between said enhancement mode transistor and said load; a second field-effect transistor having a threshold voltage approximately equal to zero volts, said second transistor coupled in series with said enhancement mode transistor and said load, the gate of said second transistor coupled to receive a timing signal; whereby, by the application of said timing signal to said gate of said second transistor, substantially no voltage drop loss occurs in said stage across said second transistor, and whereby, when said timing signal is removed from said gate of said second transistor, current flow in said stage is reduced, thereby reducing the power consumed by said stage.
Claim 2
Dependent Claim
148 words
A stage for a metal-oxide-semiconductor (MOS) buffer comprising: an enhancement mode, field-effect transistor having a gate coupled to receive an input signal for said stage; a load coupled in series with said enhancement mode transistor for providing an output signal from said stage between said enhancement mode transistor and said load; a second field-effect transistor having a threshold voltage approximately equal to zero volts, said second transistor coupled in series with said enhancement mode transistor and said load, the gate of said second transistor coupled to receive a timing signal; whereby, by the application of said timing signal to said gate of said second transistor, substantially no voltage drop loss occurs in said stage across said second transistor, and whereby, when said timing signal is removed from said gate of said second transistor, current flow in said stage is reduced, thereby reducing the power consumed by said stage.
Claim 3
Dependent Claim
16 words
The MOS buffer stage defined by claim 1 wherein said load comprises a depletion mode transistor.
Claim 4
Dependent Claim
92 words
In a metal-oxide-semiconductor (MOS) buffer which includes a depletion mode transistor coupled in series with an enhancement mode transistor where the gate of said enhancement mode transistor is coupled to receive an input signal, an improvement comprising: a field-effect transistor having a threshold voltage approximately equal to zero volts coupled in series with said enhancement mode transistor and said depletion mode transistor; whereby, by the selective application of a timing signal to the gate of said field-effect transistor, power in said buffer is reduced without substantially effecting the performance of said buffer.
Claim 5
Dependent Claim
92 words
In a metal-oxide-semiconductor (MOS) buffer which includes a depletion mode transistor coupled in series with an enhancement mode transistor where the gate of said enhancement mode transistor is coupled to receive an input signal, an improvement comprising: a field-effect transistor having a threshold voltage approximately equal to zero volts coupled in series with said enhancement mode transistor and said depletion mode transistor; whereby, by the selective application of a timing signal to the gate of said field-effect transistor, power in said buffer is reduced without substantially effecting the performance of said buffer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-07-24 | 1982-01-23 | 1982-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-07-24 | 1986-01-23 | 1986-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-07-24 | 1990-01-23 | 1990-07-25 | $7700.00 | Window Closed / Lapsed |