Integrated threshold mnos memory with decoder and operating sequence

Claim 2

A digital memory system comprising, an array of variable threshold insulated gate field effect memory transistors having source, drain, and gate electrodes, said memory transistors being arranged in word rows and bit columns on a common substrate, said memory transistors being characterized in that they display a conduction threshold which may be shifted to a high level by the application of a WRITE voltage across the gate insulator of the transistor and to a low level by the application of an inverted WRITE voltage across the gate insulator, said transistors being further characterized in that information may be read out of said transistor by application of an intermediate-valued READ voltage across the gate insulator, a source of gate voltages for the memory transistors in said array, said source including means to provide voltages of READ or WRITE magnitude to individual word rows as desired, means to apply a desired voltage to said substrate, individual bit storage registers corresponding to each bit column in the memory array, holding means in each storage register for temporarily retaining information to be stored in a selected memory transistor in the associated bit column, means for optionally coupling said holding means to either the source or drain electrodes of all memory transistors in the associated bit column, means in each bit storage register for optionally connecting the drain electrodes of all memory transistors in the associated bit column to said common substrate, means for simultaneously applying a fWRITE voltage to a selected word row from said source of gate voltages, for coupling each of said holding means to the source electrodes of the associated memory transistors, and for grounding the drain electrodes of all memory transistors so that information being stored in the memory transistor in the selected word row is loaded into the associated holding means, means for simultaneously applying a WRITE voltage to a selected word row from said source of gate voltages, for decoupling said holding means from said source and drain electrodes, and for grounding all of said drain lines so that the conduction thresholds of the memory transistors in the selected word row are preset to said high level, means for simultaneously applying a zero voltage and a WRITE voltage from said source of gate voltages to selected and unselected word rows respectively, for decoupling said holding means from said source and drain electrodes and for applying a WRITE voltage to said substrate so that the conduction thresholds of all of the memory transistors in the selected row are cleared to said low level, means for simultaneously applying a WRITE voltage to the memory transistors in a selected word row, for coupling said holding means to the drain electrodes of the memory transistors in the respective bit columns so that each memory transistor in the selected word row is exposed to a gate insulator voltage in accordance with the information being held in the corresponding holding means.

Claim 3

The memory system of claim 1 further including a source of control signals for controlling the mode of operation of components in the memory system, said memory system further being characterized in that said source of gate voltages includes word line decoder means for selecting a particular word row in the memory array in accordance with received binary address signals and buffer means for determining the magnitude of the voltages to be applied to word rows selected by said decoder means, said decoder means further including logic means for providing relatively high and low level signals to selected and unselected word rows, respectively, in response to first combination of control signals and for reversing the relative magnitude of the word row signals in response to a second combination of control signals.

Claim 4

The memory system of claim 2 wherein said source of control signals includes a multiple voltage d.c. source and control means for switching selected voltages from said d.c. source to various components in the memory system so as to provide control signals for these components.

Claim 5

The memory system of claim 3 wherein said buffer means includes means to limit said relatively high level word row signal to a voltage of READ magnitude in response to a buffer control signal of one value and to limit said high level word row signal to a voltage of WRITE magnitude in response to a buffer control signal of another value.

Claim 6

The memory system of claim 4 in which said word line decoder means is a multiple NOR gate binary decoder arranged so that each decoder output line is coupled to a first bus from said control means through a different plurality of decoder field effect transistors, said decoder being further arranged so that all decoder field effect transistor coupled to a given decoder output line are driven to cutoff only when the decoder output line corresponds to a received word line address signal, each of said decoder output lines being further coupled to a second bus from said control means through a separate logic transistor, each of said logic transistors having a gate electrode connected to said control means through a third bus, said first and second combinations of control signals being applied to said first, second and third buses.

Claim 7

The memory system of claim 5 wherein the control signals in said first combination are proportioned so as to provide a relatively high voltage only on the unselected decoder output lines and the control signals in said second coMbination are proportioned to provide a relatively high voltage only on the selected decoder output line, and wherein said decoder buffer includes means to provide word line voltages that represent the complement of the respective decoder output voltages.

Claim 8

The memory system of claim 6 further including a bit line decoder and an I/O buffer for coupling external circuitry to a bit column selected by said bit line decoder in accordance with a received bit line address signal.

Claim 9

The memory system of claim 7 wherein the I/O buffer is coupled to the holding means in each bit storage register through separate buffer-decoder field effect transistors, each of said buffer-decoder field effect transistors having a gate electrode separately and selectively actuated by said bit line decoder, said I/O buffer including terminal means for connection to external circuitry, said I/O buffer further containing first gating means for reading information out of the holding means and into external circuitry through said terminal means and second gating means for reading information out of external circuitry and into said holding means through said terminal means.

Claim 10

A digital memory system comprising an array of variable threshold insulated gate field effect memory transistors having source, drain, and gate electrodes, said memory transistors being arranged in word rows and bit columns on a common substrate, said memory transistors being characterized in that they display conduction thresholds which can be shifted to first and second levels by the application of gate voltages of first and second predetermined magnitudes, respectively, a multiple voltage d.c. source, control means for switching voltages from said d.c. source to selected components in said system so as to provide control signals for said components, word line decoder means for selecting a different row of memory transistors for each value of binary address signal applied to said decoder, said word line decoder means including logic means for producing high or low level decoder output signals for the selected row of memory transistors and low or high level signals for the unselected rows in response to first and second combinations of control signals, respectively, from said control means, word line buffer means for converting the word line decoder output signals to appropriate word line voltages for the gate electrodes of the memory transistors, said buffer means including means to invert the level of the word line decoder output signal and means to adjust the amplitude of the resulting high level word line voltages in response to buffer control signals from said control means, means for driving said source line and said drive line transistors into conduction in response to load control signals from said control means so as to couple said bit storage registers to the corresponding bit column and thereby provide information to be read out of the selected row of memory transistors and into the storage registers, means for applying said second combination of control signals to said word line decoder and an intermediate level buffer control signal to the adjustment means in said word line buffer such that the resulting selected word line voltage lies between said first and second predetermined magnitudes during the occurrence of a load control signal whereby information is read out of each memory transistor in the selected word line and into the bit storage register in accordance with the level of the conduction threshold in the transistor, means in said storage register for grounding the drain lines of all memory transistors in response to a present control signal and simultaneously isolating each holding means from the memory transistors, means to apply said second combination of signals to said word line decoder and a high level buffer control signal to the adjustment means in said word line buffer during the occurrence of a preset control signal, said high level buffer control signal having a magnitude such that the resulting selected word line voltage exceeds the larger of said first and second predetermined magnitudes whereby the conduction thresholds of all memory transistors in the selected word line are shifted to the larger of said first and second levels, means to apply said first combination of control signals to said word line decoder and a high level buffer control signal to the adjustment means in said word line buffer whereby a low level signal is applied to the selected word line and a voltage equal to the larger of said first and second predetermined magnitudes is applied to the unselected word lines, means to supply a control signal to said substrate having a magnitude and polarity equal to the voltage applied to the selected word line during the occurrence of said first combination of control signals whereby the memory transistors in the selected word row are subjected to a reverse polarity voltage equal to the larger of said first and second predetermined magnitudes and the memory transistors in the unselected word rows are subjected to low voltage so that the thresholds of all memory transistors in the selected row are set to the smaller of said first and second levels, means to couple each temporary holding means to the drain line in the corresponding memory bit column and to decouple the holding means from the corresponding source line in response to a store control signal from said control means so that the conducting channels in the memory transistor are charged to a voltage indicative of the information being retained in the respective holding means, means to apply said second combination of signals to said word line decoder and a high level buffer control signal to the adjustment means in said word line buffer during the occurrence of a store control signal so that the gate electrodes of the memory transistors in the selected row are at a high voltage and those in the unselected row are at a low voltage whereby the memory transistors in the selected word line are subjected to net gate voltages in accordance with the information being temporarily stored in the corresponding holding means.

Claim 11

A digital memory system comprising an array of variable threshold insulated gate field effect memory transistors having source, drain, and gate electrodes, said memory transistors being arranged in word rows and bit columns on a common substrate, said memory transistors being characterized in that they display conduction thresholds which can be shifted to first and second levels by the application of gate voltages of first and second predetermined magnitudes, respectively, a multiple voltage d.c. source, control means for switching voltages from said d.c. source to selected components in said system so as to provide control signals for said components, word line decoder means for selecting a different row of memory transistors for each value of binary address signal applied to said decoder, said word line decoder means including logic means for producing high or low level decoder output signals for the selected row of memory transistors and low or high level signals for the unselected rows in response to first and second combinations of control signals, respectively, from said control means, word line buffer means for converting the word line decoder output signals to appropriate word line voltages for the gate electrodes of the memory transistors, said buffer means including means to invert the level of the word line decoder output signal and means to adjust the amplitude of the resulting high level word line voltages in response to buffer control signals from said control means, means for driving said source line and said drive line transistors into conduction in response to load control signals from said control means so as to couple said bit storage registers to the corresponding bit column and thereby provide information to be read out of the selected row of memory transistors and into the storage registers, means for applying said second combination of control signals to said word line decoder and an intermediate level buffer control signal to the adjustment means in said word line buffer such that the resulting selected word line voltage lies between said first and second predetermined magnitudes during the occurrence of a load control signal whereby information is read out of each memory transistor in the selected word line and into the bit storage register in accordance with the level of the conduction threshold in the transistor, means in said storage register for grounding the drain lines of all memory transistors in response to a present control signal and simultaneously isolating each holding means from the memory transistors, means to apply said second combination of signals to said word line decoder and a high level buffer control signal to the adjustment means in said word line buffer during the occurrence of a preset control signal, said high level buffer control signal having a magnitude such that the resulting selected word line voltage exceeds the larger of said first and second predetermined magnitudes whereby the conduction thresholds of all memory transistors in the selected word line are shifted to the larger of said first and second levels, means to apply said first combination of control signals to said word line decoder and a high level buffer control signal to the adjustment means in said word line buffer whereby a low level signal is applied to the selected word line and a voltage equal to the larger of said first and second predetermined magnitudes is applied to the unselected word lines, means to supply a control signal to said substrate having a magnitude and polarity equal to the voltage applied to the selected word line during the occurrence of said first combination of control signals whereby the memory transistors in the selected word row are subjected to a reverse polarity voltage equal to the larger of said first and second predetermined magnitudes and the memory transistors in the unselected word rows are subjected to low voltage so that the thresholds of all memory transistors in the selected row are set to the smaller of said first and second levels, means to couple each temporary holding means to the drain line in the corresponding memory bit column and to decouple the holding means from the corresponding source line in response to a store control signal from said control means so that the conducting channels in the memory transistor are charged to a voltage indicative of the information being retained in the respective holding means, means to apply said second combination of signals to said word line decoder and a high level buffer control signal to the adjustment means in said word line buffer during the occurrence of a store control signal so that the gate electrodes of the memory transistors in the selected row are at a high voltage and those in the unselected row are at a low voltage whereby the memory transistors in the selected word line are subjected to net gate voltages in accordance with the information being temporarily stored in the corresponding holding means.