Low power dissipation combined enhancement depletion switching driver circuit

Claim 2

A push-pull inverter circuit comprising in combination: first and second inverters, each including at least one depletion-type load field-effect transistor and one enhancement type driving field-effect transistor; a third inverter having an extremely small load impedance with respect to those of said first and second inverters and including at least one depletion-type load field-effect transistor and one enhancement-type driving field-effect transistor; input terminals of the respective inverters being connected to a common input line; the gate and drain of the load field-effect transistor of said first inverter being short-circuited;

Claim 3

an output terminal of said first inverter being connected to the gate of the load field-effect transistor of said second inverter; an output terminal of said second inverter being connected to the gate of the load field-effect transistor of said third inverter; and an output terminal of said third inverter providing an output of the circuit.

Claim 4

an output terminal of said first inverter being connected to the gate of the load field-effect transistor of said second inverter; an output terminal of said second inverter being connected to the gate of the load field-effect transistor of said third inverter; and an output terminal of said third inverter providing an output of the circuit.

Claim 5

The push-pull output inverter circuit according to claim 1, in which each of the load field-effect transistors in said first and second inverters has a width to length ratio of the channel region considerably smaller than that of the load field-effect transistor in said third inverter.

Claim 6

A combined enhancement-depletion switching driver circuit comprising: a first inverter stage including a first driving enhancement metal-insulator-semiconductor transistor and a first load depletion metal-insulator-semiconductor transistor connected in series with a source of supply voltage, the gate and the drain of said first load transistor being coupled together; a second inverter stage including a second driving enhancement metal-insulator-semiconductor transistor and a second load depletion metal-insulator-semiconductor transistor connected in series with said source of supply voltage, an output node of said first inverter being coupled to the gate of said second load transistor; a third inverter stage including a third enhancement driving metal-insulator-semiconductor transistor and a third load depletion metal-insulator-semiconductor transistor connected in series with said source of supply voltage and providing an output of the circuit, an output node of said second inverter stage being coupled to the gate of said third load transistor; the gates of said first, second and third driving transistors being coupled to receive an input in common, and the impedance of each of said first and second load transistors being considerably higher than that of said third load transistor so that when the driving transistors are conductive, currents through said first and second load transistors are negligible with respect to that through said third load transistor.

Claim 7

A combined enhancement-depletion switching driver circuit comprising: a first inverter stage including a first driving enhancement metal-insulator-semiconductor transistor and a first load depletion metal-insulator-semiconductor transistor connected in series with a source of supply voltage, the gate and the drain of said first load transistor being coupled together; a second inverter stage including a second driving enhancement metal-insulator-semiconductor transistor and a second load depletion metal-insulator-semiconductor transistor connected in series with said source of supply voltage, an output node of said first inverter being coupled to the gate of said second load transistor; a third inverter stage including a third enhancement driving metal-insulator-semiconductor transistor and a third load depletion metal-insulator-semiconductor transistor connected in series with said source of supply voltage and providing an output of the circuit, an output node of said second inverter stage being coupled to the gate of said third load transistor; the gates of said first, second and third driving transistors being coupled to receive an input in common, and the impedance of each of said first and second load transistors being considerably higher than that of said third load transistor so that when the driving transistors are conductive, currents through said first and second load transistors are negligible with respect to that through said third load transistor.

Claim 8

A switching driver circuit comprising, in combination: an input terminal; a supply voltage terminal; a reference voltage terminal; an output terminal; a first inverter stage comprising a first enhancement mode driving field-effect transistor and a first depletion mode load fielf-effect transistor having their source-drain paths connected in series between said voltage terminals, the gate and drain of said first depletion mode transistor being connected in common; a second inverter stage comprising a second enhancement mode driving field-effect transistor and a second depletion mode load field-effect transistor having their source-drain paths connected in series between said voltage terminals, the juncture of said first transistors of said stage being connected to the gate of said second load transistor; a third inverter stage comprising a third enhancement mode driving field-effect transistor and a third depletion mode load field-effect transistor having their source-drain paths connected in series between said voltage terminals, the juncture of the second transistors of said second stage being connected to the gate of said third load transistor and the juncture of the third transistors of said third stage being connected to said output terminal; said input terminal being connected in common to the gates of each of said first, second and third enhancement mode transistors; and wherein the width to length ratio of the channel region of said third load transistor is more than two orders of magnitude as large as that of said first and second load transistors.

Claim 9

A switching driver circuit comprising, in combination: an input terminal; a supply voltage terminal; a reference voltage terminal; an output terminal; a first inverter stage comprising a first enhancement mode driving field-effect transistor and a first depletion mode load fielf-effect transistor having their source-drain paths connected in series between said voltage terminals, the gate and drain of said first depletion mode transistor being connected in common; a second inverter stage comprising a second enhancement mode driving field-effect transistor and a second depletion mode load field-effect transistor having their source-drain paths connected in series between said voltage terminals, the juncture of said first transistors of said stage being connected to the gate of said second load transistor; a third inverter stage comprising a third enhancement mode driving field-effect transistor and a third depletion mode load field-effect transistor having their source-drain paths connected in series between said voltage terminals, the juncture of the second transistors of said second stage being connected to the gate of said third load transistor and the juncture of the third transistors of said third stage being connected to said output terminal; said input terminal being connected in common to the gates of each of said first, second and third enhancement mode transistors; and wherein the width to length ratio of the channel region of said third load transistor is more than two orders of magnitude as large as that of said first and second load transistors.

Claim 10

A switching driver circuit according to claim 4, wherein the impedances of said first and second load transistors are in excess of two orders of magnitude as large as that of said third load transistor.