US3775693A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mosfet logic inverter for integrated circuits
Assignee: Thomson Components-Mostek Corp
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Filing: 1971-11-29
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Granted: 1973-11-27
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Expires: 1991-11-29
Abstract
Abstract The specification discloses a logic inverter comprised of a depletion mode MOSFET used as a resistive load between a drain supply voltage and an output and one or more enhancement mode MOSFET''s connected between output and source supply voltage. The source and gate of the depletion mode device are electrically common, and the gates of the enhancement mode devices form the logic inputs. The use of one enhancement mode device provides a simple inverter, a plurality of enhancement mode devices in parallel form a NOR gate, and a plurality of enhancement mode devices in series form a NAND gate. Combination NOR and NAND GATES may also be formed. The basic inverter circuit is also combined with a push-pull output stage to provide increased speed of operation, particularly at higher drain supply voltages. Still another embodiment utilizes an enhancement mode transistor connected between the depletion mode transistor and the output of the basic inverter stage to provide a disable function in which output drain current is switched off under all logic input conditions.
Inventors
- 👤 R Proebsting
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:49
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/84; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09441; H03K19/09443; H03K19/09445
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
106 words
The integrated circuit including the inverter gate comprising: a depletion mode field effect transistor coupling a drain voltage to an output node, the gate of the depletion mode field effect transistor being connected to the output node, at least one enhancement mode field effect transistor coupling the output node to a source voltage, the gate of the enhancement mode transistor being the input, and at least one enhancement mode field effect transistor coupling the source of the depletion mode field effect transistor to the output node, the gate of said last mentioned enhancement mode field effect transistor being a logic input for enabling the inverter gate.
Claim 2
Dependent Claim
106 words
The integrated circuit including the inverter gate comprising: a depletion mode field effect transistor coupling a drain voltage to an output node, the gate of the depletion mode field effect transistor being connected to the output node, at least one enhancement mode field effect transistor coupling the output node to a source voltage, the gate of the enhancement mode transistor being the input, and at least one enhancement mode field effect transistor coupling the source of the depletion mode field effect transistor to the output node, the gate of said last mentioned enhancement mode field effect transistor being a logic input for enabling the inverter gate.
Claim 3
Dependent Claim
14 words
The integrated circuit of claim 1 wherein all field effect transistors are p-channel devices.
Claim 4
Dependent Claim
14 words
The integrated circuit of claim 1 wherein all field effect transistors are n-channel devices.
Claim 5
Dependent Claim
146 words
The integrated circuit including the inverter circuit comprising: a first depletion mode field effect transistor coupling a drain voltage to a first output node, the gate of the first depletion mode field effect transistor being connected to the first output node, a first enhancement mode field effect transistor coupling the first output node to a source voltage, the gate of the first enhancement mode field effect transistor being connected to an input terminal, a second depletion mode field effect transistor coupling a drain voltage to a second output node, the gate of the second depletion mode field effect transistor being connected to the first output node, and a second enhancement mode field effect transistor coupling the second output node to a source voltage, the gate of the second enhancement mode field effect transistor being connected to the gate of the first enhancement mode field effect transistor.
Claim 6
Dependent Claim
146 words
The integrated circuit including the inverter circuit comprising: a first depletion mode field effect transistor coupling a drain voltage to a first output node, the gate of the first depletion mode field effect transistor being connected to the first output node, a first enhancement mode field effect transistor coupling the first output node to a source voltage, the gate of the first enhancement mode field effect transistor being connected to an input terminal, a second depletion mode field effect transistor coupling a drain voltage to a second output node, the gate of the second depletion mode field effect transistor being connected to the first output node, and a second enhancement mode field effect transistor coupling the second output node to a source voltage, the gate of the second enhancement mode field effect transistor being connected to the gate of the first enhancement mode field effect transistor.
Claim 7
Dependent Claim
14 words
The integrated circuit of claim 4 wherein the field effect transistors are p-channel devices.
Claim 8
Dependent Claim
14 words
The integrated circuit of claim 4 wherein the field effect transistors are n-channel devices.
References Cited (Backward Citations)
US3436621A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-11-26 | 1977-05-28 | 1977-11-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-11-26 | 1981-05-28 | 1981-11-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-11-26 | 1985-05-28 | 1985-11-27 | $7700.00 | Window Closed / Lapsed |