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US4021656A Expired / Lapsed US ⏱️ 0.0 years remaining

Data input for electronic calculator or digital processor chip

Assignee: Texas Instruments Inc
•
Filing: 1974-11-19
•
Granted: 1977-05-03
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Expires: 1994-11-19
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Abstract

Abstract An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a RAM for data storage, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. The operation is digit oriented in that in a machine cycle one digit of the RAM is accessed, and also the ROM is addressed to provide an instruction word which is decoded and executed. The data input to the system is by four parallel lines which may be connected to a scanned keyswitch matrix or to BCD or binary data sources. Within the chip, the data inputs may be coupled to the input of the arithmetic unit, or to the data memory directly. ______________________________________ Table of Contents ______________________________________ Subject Page ______________________________________ Related Cases 2 Background of the Invention 2 Summary of the Invention 3 Brief Description of the Drawings 5 Detailed Description of Specific Embodiment 7 The Overall System 7 The System Block Diagram 10 System Timing 17 The Data Memory 18 The Adder 21 The Adder Input Select 23 The Accumulator and RAMY Y Registers 24 The Data Path Control PLA 24 The Status Logic and Status Latch 26 Generating the ROM Address 27 The Program Counter 28 The Subroutine Register 29 The ROM Page Address Register and Buffer 30 The Address Controls 32 The Keyboard Input 34 The Control-Keyboard-Bit Logic 35 The RAM Page Address 36 The ROM and ROM Page Address Decoder 39 The ROM/RAM Word Decoder 41 The D Output Register 44 The Accumulator Output Register and Segment Decoder 45 The Power-Up-Clear Circuit 46 The Program Counter Feedback 47 The Clock Generator 48 Details of Logic Blocks 49 The Instruction Set 49 Instruction Word Execution Timing 54 The MOS/LSI Chip 55 The Chip Test Functions 56 Table of Instructions 60 ______________________________________

Inventors

  • 👤 Edward R. Caudel
  • 👤 Joseph H. Raymond, Jr.

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 22:26
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/402

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 132 words
In an electronic calculator system of the type having data storage means, a read-only-memory for storing program instructions, an arithmetic unit for performing operations on data, control circuitry receiving program instructions from the read-only-memory and providing commands for defining the operation of the system, multiple digit display means, means for applying representations of data from the data storage means and sequential pulses to the display means, the sequential pulses and the representations of data being in time multiplex, keyboard means having inputs receiving the sequential pulses and having a plurality of outputs, the improvement wherein: coupling means connects the outputs of the keyboard directly to the input of the arithmetic means, and means connecting the control means to the coupling means whereby the coupling means operates under command of the control means.
Claim 2
Dependent Claim 132 words
In an electronic calculator system of the type having data storage means, a read-only-memory for storing program instructions, an arithmetic unit for performing operations on data, control circuitry receiving program instructions from the read-only-memory and providing commands for defining the operation of the system, multiple digit display means, means for applying representations of data from the data storage means and sequential pulses to the display means, the sequential pulses and the representations of data being in time multiplex, keyboard means having inputs receiving the sequential pulses and having a plurality of outputs, the improvement wherein: coupling means connects the outputs of the keyboard directly to the input of the arithmetic means, and means connecting the control means to the coupling means whereby the coupling means operates under command of the control means.
Claim 3
Dependent Claim 51 words
A system according to claim 1 wherein the system includes an accumulator register, and the output of the arithmetic unit is selectively connected to the accumulator register under control of the control means, and the accumulator register is selectively connected to the data storage means under control of the control means.
Claim 4
Dependent Claim 55 words
A system according to claim 2 wherein the system includes a register having its output coupled to the input of the arithmetic unit, and a representation of the particular one of said sequential pulses occurring at a given time is stored in said register which is selectively applied to the input of the arithmetic unit.
Claim 5
Dependent Claim 60 words
A system according to claim 3 wherein data is stored in the data storage means in digits of four bits, the arithmetic unit is arranged in four bit parallel format, the accumulator register is four parallel bits, the register containing the representation of the sequential pulse is in four parallel bits, and there are four parallel outputs from the keyboard.
Claim 6
Dependent Claim 26 words
A system according to claim 4 wherein the outputs from the keyboard are alternatively coupled to the data storage means under control of the control means.
Claim 7
Dependent Claim 39 words
A system according to claim 1 wherein the arithmetic unit under control of the control means performs a compare function and a constant is selectively connected to the input of the arithmetic unit under control of the control means.
Claim 8
Dependent Claim 196 words
In an electronic digital processor system of the type implemented in MOS/LSI semiconductor means and having data storage means including a random access memory, first addressing means coupled to the data storage means for accessing data therein, program storage means including a read-only-memory containing a large number of instruction words, second addressing means coupled to the program storage means for accessing instruction words, arithmetic means for performing arithmetic operations on input digits applied thereto, control means receiving the instruction words from the read-only-memory and generating command signals for defining the operation of the system, timing means for the system generating a recurring machine cycle of fixed length, the random access memory being accessed and the read-only-memory being accessed during such machine cycle and the control means receiving an instruction word to generate commands as well as the arithmetic means receiving an input during such machine cycle the improvement wherein the system includes a plurality of parallel input terminals and data input to the system is provided by said plurality of parallel input terminals, and means are provided for selectively connecting the input terminals to the input of the arithmetic means and to the data storage means.
Claim 9
Dependent Claim 196 words
In an electronic digital processor system of the type implemented in MOS/LSI semiconductor means and having data storage means including a random access memory, first addressing means coupled to the data storage means for accessing data therein, program storage means including a read-only-memory containing a large number of instruction words, second addressing means coupled to the program storage means for accessing instruction words, arithmetic means for performing arithmetic operations on input digits applied thereto, control means receiving the instruction words from the read-only-memory and generating command signals for defining the operation of the system, timing means for the system generating a recurring machine cycle of fixed length, the random access memory being accessed and the read-only-memory being accessed during such machine cycle and the control means receiving an instruction word to generate commands as well as the arithmetic means receiving an input during such machine cycle the improvement wherein the system includes a plurality of parallel input terminals and data input to the system is provided by said plurality of parallel input terminals, and means are provided for selectively connecting the input terminals to the input of the arithmetic means and to the data storage means.
Claim 10
Dependent Claim 23 words
A system according to claim 7 including an accumulator register and means for connecting the accumulator to the output of the arithmetic means.
Claim 11
Dependent Claim 42 words
A system according to claim 7 wherein the arithmetic means includes compare circuitry producing a compare output in response to the command signals from the control means, and means are provided to couple a constant to the input of the arithmetic means.

References Cited (Backward Citations)

US3800129A Cited
US3760171A Cited
US3715746A Cited
US3863060A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-05-02 1980-11-01 1981-05-03 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-05-02 1984-11-01 1985-05-03 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-05-02 1988-11-01 1989-05-03 $7700.00 Window Closed / Lapsed

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