High current static MOS output buffer circuit for power-down mode of operation

Claim 2

In a circuit having an output transistor including a current path and a control electrode, a circuit input coupled to said control electrode to turn said current path on and off, an output node, and means connecting the current path of the output transistor between a voltage supply and said output node, the improvement comprising: a pair of transistors having parallel current paths and a common control electrode, means connecting said parallel current paths between said voltage supply and said control electrode of said output transistor, one of said pair of transistors having a threshold voltage of the polarity of said voltage supply and the other having a threshold voltage which is zero or a small voltage of the opposite polarity.

Claim 3

A circuit according to claim 1 wherein said transistors are N-channel field effect transistors, the current paths are source-to-drain paths, and said control electrodes are gates.

Claim 4

A circuit according to claim 2 wherein said output transistor has a threshold voltage of about the same magnitude and polarity as that of the threshold voltage of said one of said pair of transistors.

Claim 5

A circuit according to claim 3 wherein a second output transistor has a current path connected in parallel series with that of said output transistor and has a threshold voltage substantially of the same polarity and greater than that of the threshold voltage of said one of said pair of transistors.

Claim 6

A circuit according to claim 3 wherein the gates of said pair of transistors are connected to a "chip select" voltage which is high when the circuit is in a selected mode and is zero when the circuit is in a not-selected mode and also is zero when the circuit is in a power-down mode.

Claim 7

A circuit according to claim 5 wherein said pair of transistors share common channel, source and drain areas in a face of a semiconductor body, except that the area of the channel of said one of the pair of transistors is implanted to provide depletion mode operation.

Claim 8

A circuit according to claim 6 wherein said one of said pair of transistors has a channel width much smaller than said other of said pair.

Claim 9

A circuit according to claim 7 wherein said implant area of said one of the pair of transistors is centrally located in the channel of said other of the pair of transistors.

Claim 10

A circuit according to claim 1 wherein another transistor has a current path connected between the control electrode of said output transistor and reference potential and has a control electrode connected to the complement of the signal which is on the common control electrodes of said pair of transistors.

Claim 11

In a circuit having an input, a first output transistor and a second output transistor, each output transistor having a current path and a control electrode, an output node, means connecting the current path of the first output transistor in series between a voltage supply and said output node, means connecting the current path of the second output transistor between said output node and reference potential, and circuit input means for coupling said input to the control electrode of one of the first and second output transistors and coupling the complement of said input to the control electrode of the other of said first and second output transistors, the improvement comprising a pair of transistors having parallel current paths and a common control electrode, means connecting said parallel current paths between said voltage supply and said control electrode of said first output transistor, one of said pair of transistors having a threshold voltage of the polarity of said voltage supply and the other having a threshold voltage which is zero or a small voltage of the opposite polarity.

Claim 12

In a circuit having an input, a first output transistor and a second output transistor, each output transistor having a current path and a control electrode, an output node, means connecting the current path of the first output transistor in series between a voltage supply and said output node, means connecting the current path of the second output transistor between said output node and reference potential, and circuit input means for coupling said input to the control electrode of one of the first and second output transistors and coupling the complement of said input to the control electrode of the other of said first and second output transistors, the improvement comprising a pair of transistors having parallel current paths and a common control electrode, means connecting said parallel current paths between said voltage supply and said control electrode of said first output transistor, one of said pair of transistors having a threshold voltage of the polarity of said voltage supply and the other having a threshold voltage which is zero or a small voltage of the opposite polarity.

Claim 13

A circuit according to claim 10 wherein said first and second output transistors and said pair of transistors are all insulated-gate field effect transistors, the current paths are source-to-drain paths, and said control electrodes are gates.

Claim 14

A circuit according to claim 11 wherein said first output transistor has a threshold voltage of about the same magnitude and polarity as that of the threshold voltage of said one of said pair of transistors.

Claim 15

A circuit according to claim 12 wherein said second output transistor has a threshold voltage substantially of the same polarity and greater in magnitude than the threshold voltage of said one of said pair of transistors.

Claim 16

A circuit according to claim 11 wherein the gates of said pair of transistors are connected to a "chip select" voltage which is high when the circuit is in a selected mode and is zero when the circuit is in a not-selected mode and also is zero when the circuit is in a power-down mode.

Claim 17

A circuit according to claim 11 wherein said pair of transistors share common channel, source and drain areas in a face of a semiconductor body, except that the area of the channel of said one of the pair of transistors is implanted to provide depletion mode operation.

Claim 18

A circuit according to claim 11 including third and fourth transistors each having a current path connected between the control electrode of one of said first and second output transistors respectively and reference potential, and each of the third and fourth transistors has a control electrode connected to the complement of the signal which is on the common control electrodes of said pair of transistors.