US4051388A — Flip-flop accompanied by two current switches, on…

Claim 1

Independent Claim 252 words

A circuit arrangement comprising: a flip-flop circuit including a first field-effect transistor having a first electrode connected to a common point, a second electrode connected to a first node, and a control electrode connected to a second node, a second field-effect transistor having a first electrode connected to said common point, a second electrode connected to said second node, and a control electrode connected to said first node, and a third field-effect transistor having a first electrode connected to a reference point, a second electrode connected to said common point, and a control electrode connected to a source of an activation signal; precharge means connected to said first and second nodes for rendering said first node voltage higher than said second node voltage when said flip-flop circuit is in quiescent state; a first current switching circuit including a fourth field-effect transistor having a first electrode connected to said reference point, a second electrode connected to said first node, and a control electrode connected to an input terminal; and a second current switching circuit including a fifth field effect transistor having a first electrode, a second electrode connected to said second node, and a control electrode connected to said first node, and a sixth field-effect transistor having a first electrode connected to said reference point, a second electrode connected to said first electrode of said fifth transistor, and control electrode connected to the source of said activation signal; said second switching circuit having a smaller current sink capability than said first switching circuit.

Claim 2

Dependent Claim 252 words

A circuit arrangement comprising: a flip-flop circuit including a first field-effect transistor having a first electrode connected to a common point, a second electrode connected to a first node, and a control electrode connected to a second node, a second field-effect transistor having a first electrode connected to said common point, a second electrode connected to said second node, and a control electrode connected to said first node, and a third field-effect transistor having a first electrode connected to a reference point, a second electrode connected to said common point, and a control electrode connected to a source of an activation signal; precharge means connected to said first and second nodes for rendering said first node voltage higher than said second node voltage when said flip-flop circuit is in quiescent state; a first current switching circuit including a fourth field-effect transistor having a first electrode connected to said reference point, a second electrode connected to said first node, and a control electrode connected to an input terminal; and a second current switching circuit including a fifth field effect transistor having a first electrode, a second electrode connected to said second node, and a control electrode connected to said first node, and a sixth field-effect transistor having a first electrode connected to said reference point, a second electrode connected to said first electrode of said fifth transistor, and control electrode connected to the source of said activation signal; said second switching circuit having a smaller current sink capability than said first switching circuit.

Claim 3

Dependent Claim 41 words

The circuit arrangement as claimed in claim 1, in which said transistors are formed on the same semiconductor chip and at least one of said fifth and sixth transistors occupies a smaller area on said semiconductor chip than said fourth transistor.

Claim 4

Dependent Claim 66 words

The circuit arrangement as claimed in claim 1 further comprising; additional current switching circuit including, in turn, additional field-effect transistors, respectively, each having a first electrode connected to said reference point, a second electrode connected to said first node, and a control electrode connected to an additional input terminal, each of said additional switching circuits having a larger current sink capability than said second switching circuit.

Claim 5

Dependent Claim 94 words

A circuit arrangement as claimed in claim 1, wherein said precharge means comprises a seventh field-effect transistor having a first electrode connected to said first node, a second electrode connected to a power source, and a control electrode, first means for supplying a first voltage to the control electrode of said seventh transistor, an eighth field-effect transistor having a first electrode connected to said second node, a second electrode connected to said power source, and a control electrode, and second means for supplying a second voltage to the control electrode of said eighth transistor.

Claim 6

Dependent Claim 42 words

The circuit arrangement as claimed in claim 4, wherein said first and second voltages have values capable of making said seventh and eighth transistors conductive, respectively, and the absolute value of said first voltage is higher than that of said second voltage.

Claim 7

Dependent Claim 45 words

A circuit arrangement as claimed in claim 4, wherein said second means comprises a ninth field effect transistor having a first electrode connected to the control electrode of said eighth transistor, a second electrode and a control electrode connected in common to said power source.

Claim 8

Dependent Claim 223 words

In combination, a flip-flop circuit residing in one of a quiescent state in which direct current conduction is eliminated in said flip-flop circuit and an activated state, said flip-flop including first and second nodes, first and second field-effect transistors cross-coupled to each other at said first and second nodes; a first current switching circuit connected to said first node and having an input terminal for receiving an input signal; a second current switching circuit connected to said second node and having a control terminal connected to said first node and further having an activation terminal for receiving an activation signal, said second switching circuit having a smaller current sinking capability than said first switching circuit; means for switching said flip-flop circuit from said quiescent state to said activated state in response to said activation signal; means for precharging said first and second nodes to first and second potentials sufficient in amplitude to cause said first and second transistors to be in their conductive state, respectively, during said quiescent state, said first potential being higher than said second potential; whereby said first node voltage becomes opposite in its digital level to said input signal and said second node voltage becomes of substantially the same digital level as said input signal when said flip-flop circuit is switched to said activated state by said switching means.

Claim 9

Dependent Claim 223 words

In combination, a flip-flop circuit residing in one of a quiescent state in which direct current conduction is eliminated in said flip-flop circuit and an activated state, said flip-flop including first and second nodes, first and second field-effect transistors cross-coupled to each other at said first and second nodes; a first current switching circuit connected to said first node and having an input terminal for receiving an input signal; a second current switching circuit connected to said second node and having a control terminal connected to said first node and further having an activation terminal for receiving an activation signal, said second switching circuit having a smaller current sinking capability than said first switching circuit; means for switching said flip-flop circuit from said quiescent state to said activated state in response to said activation signal; means for precharging said first and second nodes to first and second potentials sufficient in amplitude to cause said first and second transistors to be in their conductive state, respectively, during said quiescent state, said first potential being higher than said second potential; whereby said first node voltage becomes opposite in its digital level to said input signal and said second node voltage becomes of substantially the same digital level as said input signal when said flip-flop circuit is switched to said activated state by said switching means.

Claim 10

Dependent Claim 211 words

A decoder circuit comprising an output node; input terminals receiving a plurality of input signals; a plurality of field-effect transistors connected in parallel between said output node and a reference potential, control gates of said transistors being coupled with said input terminals; a flip-flop circuit having a quiescent state in which direct current paths are eliminated in said flip-flop circuit and an activated state and further having a first node directly connected to said output node and a second node; a current switching circuit connected to said second node, said current switching circuit having a control terminal connected to said first node and an activation terminal for receiving an activation signal, said switching circuit having a smaller current sinking capability than said transistors; means for switching said flip-flop circuit from said quiescent state to activated state in response to said activation signal; means for precharging said first and second potentials, respectively, during said quiescent state of said flip-flop circuit, said first potential being higher than said second potential; whereby said output node directly connected to said first node becomes said reference potential when at least one of said transistors becomes the conductive state at the same time that said flip-flop circuit is switched to said activated state by said switching means.

Claim 11

Dependent Claim 211 words

A decoder circuit comprising an output node; input terminals receiving a plurality of input signals; a plurality of field-effect transistors connected in parallel between said output node and a reference potential, control gates of said transistors being coupled with said input terminals; a flip-flop circuit having a quiescent state in which direct current paths are eliminated in said flip-flop circuit and an activated state and further having a first node directly connected to said output node and a second node; a current switching circuit connected to said second node, said current switching circuit having a control terminal connected to said first node and an activation terminal for receiving an activation signal, said switching circuit having a smaller current sinking capability than said transistors; means for switching said flip-flop circuit from said quiescent state to activated state in response to said activation signal; means for precharging said first and second potentials, respectively, during said quiescent state of said flip-flop circuit, said first potential being higher than said second potential; whereby said output node directly connected to said first node becomes said reference potential when at least one of said transistors becomes the conductive state at the same time that said flip-flop circuit is switched to said activated state by said switching means.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1980-09-26	1981-03-28	1981-09-27	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1984-09-26	1985-03-28	1985-09-27	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1988-09-26	1989-03-28	1989-09-27	$7700.00	Window Closed / Lapsed

Flip-flop accompanied by two current switches, one having a smaller current sink capability than the other

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