US3987315A
Expired / Lapsed
US
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Amplifier circuit
Assignee: NEC Corp
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Filing: 1975-09-03
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Granted: 1976-10-19
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Expires: 1995-09-03
Abstract
Abstract An amplifier circuit for amplifying an input signal includes a flip-flop circuit activated by a timing signal. A trigger circuit generates a first trigger signal of the same polarity as the input signal and another circuit generates a second trigger signal of the opposite polarity to the input signal. The flip-flop circuit is triggered by the first and second trigger signals at the same time the flip-flop circuit is activated by the timing signal.
Inventors
- 👤 Shigeki Matsue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 00:41
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356086; H03K3/356095; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4082; H03K3/356017; H03K3/356026
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
336 words
An amplifier circuit for amplifying an input signal, said circuit comprising a flip-flop circuit activated by a first timing signal, a first trigger circuit for generating a first trigger signal of the same polarity as that of said input signal, and a second trigger circuit for generating a second trigger signal of the opposite polarity to that of said input signal, said flip-flop circuit including first and second insulated-gate field effect transistors each of which includes a gate terminal supplied with a second timing signal which is opposite in polarity to that of said first timing signal, and a drain terminal connected to one end of a power source; third and fourth insulated-gate field effect transistors each of which includes a gate terminal connected to the source terminals of said first and second transistors, respectively, and a drain terminal supplied with said first timing signal; fifth and sixth insulated-gate field effect transistors each including a source terminal connected to the other end of said power source, a drain terminal connected to the source terminals of said first and second transistors, respectively, and a gate terminal connected to the source terminals of said fourth and third transistors, respectively; and seventh and eighth insulated-gate field effect transistors each of which includes a source terminal connected to the other end of said power source, a drain terminal connected to the source terminals of said third and fourth transistors, respectively, and a gate terminal connected to the source terminals of said fourth and third transistors, respectively; whereby said first and second trigger signals are applied to the gate terminals of said fifth and sixth transistors, respectively, a first output signal having the same polarity as that of said input signal is derived from the drain terminal of said eighth transistor, and a second output signal having the opposite polarity to that of said input signal is derived from the drain terminal of said seventh transistor at the same time that said flip-flop circuit is activated by said first timing signal.
Claim 2
Dependent Claim
336 words
An amplifier circuit for amplifying an input signal, said circuit comprising a flip-flop circuit activated by a first timing signal, a first trigger circuit for generating a first trigger signal of the same polarity as that of said input signal, and a second trigger circuit for generating a second trigger signal of the opposite polarity to that of said input signal, said flip-flop circuit including first and second insulated-gate field effect transistors each of which includes a gate terminal supplied with a second timing signal which is opposite in polarity to that of said first timing signal, and a drain terminal connected to one end of a power source; third and fourth insulated-gate field effect transistors each of which includes a gate terminal connected to the source terminals of said first and second transistors, respectively, and a drain terminal supplied with said first timing signal; fifth and sixth insulated-gate field effect transistors each including a source terminal connected to the other end of said power source, a drain terminal connected to the source terminals of said first and second transistors, respectively, and a gate terminal connected to the source terminals of said fourth and third transistors, respectively; and seventh and eighth insulated-gate field effect transistors each of which includes a source terminal connected to the other end of said power source, a drain terminal connected to the source terminals of said third and fourth transistors, respectively, and a gate terminal connected to the source terminals of said fourth and third transistors, respectively; whereby said first and second trigger signals are applied to the gate terminals of said fifth and sixth transistors, respectively, a first output signal having the same polarity as that of said input signal is derived from the drain terminal of said eighth transistor, and a second output signal having the opposite polarity to that of said input signal is derived from the drain terminal of said seventh transistor at the same time that said flip-flop circuit is activated by said first timing signal.
Claim 3
Dependent Claim
38 words
An amplifier circuit according to claim 1, further including a first capacitor connected between the gate and source terminals of said third transistor, and a second capacitor connected between the gate and source terminals of said fourth transistor.
Claim 4
Dependent Claim
172 words
An amplifier circuit according to claim 1, wherein said first trigger circuit includes a ninth insulated gate field effect transistor having a drain terminal connected to one end of said power source, and a gate terminal supplied with said second timing signal, a tenth insulated-gate field effect transistor having a drain terminal connected to the source terminal of said ninth transistor, a gate terminal supplied with said input signal, and a source terminal connected to the other end of said power source, and an eleventh insulated-gate field effect transistor having a drain terminal connected to the gate terminal of said fifth transistor, a gate terminal connected to the drain terminal of said tenth transistor, and a source terminal connected to the other end of said power source, and said trigger circuit includes a twelfth insulated-gate field effect transistor having a drain terminal connected to the drain terminal of said sixth transistor, a gate terminal supplied with said input signal, and a source terminal connected to the other end of said power source.
Claim 5
Dependent Claim
153 words
An amplifier circuit according to claim 1, wherein said flip-flop circuit further includes ninth and tenth insulated-gate field effect transistors each of which includes a drain terminal connected to one end of said power source, and a gate terminal supplied with said first and second output signals, respectively, and eleventh and twelfth insulated-gate field effect transistors each of which includes a source terminal connected to the other end of said power source, a drain terminal connected to the source terminals of said ninth and tenth transistors, respectively, and a gate terminal connected to the gate terminals of said tenth and ninth transistors, respectively, whereby a third output signal having the same polarity as that of said input signal is derived from the drain terminal of said eleventh transistor, and a fourth output signal having the opposite polarity to that of said input signal is derived from the drain terminal of said twelfth transistor.
Claim 6
Dependent Claim
79 words
An amplifier circuit according to claim 4, further including a third trigger circuit for generating a third trigger signal of the same polarity as that of said input signal, and a fourth trigger circuit for generating a fourth trigger signal of the opposite polarity to that of said input signal, said third trigger signal being applied to the source terminal of said second transistor, and said fourth trigger circuit being applied to the source terminal of said first transistor.
Claim 7
Dependent Claim
145 words
A circuit arrangement comprising a flip-flop circuit including first and second insulated-gate field effect transistors each of which inlcudes a gate terminal supplied with a timing signal, and a drain terminal connected to a power source; third and fourth insulated-gate field effect transistors, the gate terminals thereof being connected to the source terminals of said first and second transistors, respectively; fifth and sixth insulated-gate field effect transistors, the drain terminals thereof being connected to the source terminals of said first and second transistors, respectively, and the gate terminals thereof being connected to the source terminals of said fourth and third transistors, respectively; and seventh and eighth insulated-gate field effect transistors, the drain terminals thereof being connected to the source terminals of said third and fourth transistors, respectively, and the gate terminals thereof being connected to the source terminals of said fourth and third transistors, respectively.
Claim 8
Dependent Claim
145 words
A circuit arrangement comprising a flip-flop circuit including first and second insulated-gate field effect transistors each of which inlcudes a gate terminal supplied with a timing signal, and a drain terminal connected to a power source; third and fourth insulated-gate field effect transistors, the gate terminals thereof being connected to the source terminals of said first and second transistors, respectively; fifth and sixth insulated-gate field effect transistors, the drain terminals thereof being connected to the source terminals of said first and second transistors, respectively, and the gate terminals thereof being connected to the source terminals of said fourth and third transistors, respectively; and seventh and eighth insulated-gate field effect transistors, the drain terminals thereof being connected to the source terminals of said third and fourth transistors, respectively, and the gate terminals thereof being connected to the source terminals of said fourth and third transistors, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-10-19 | 1980-04-19 | 1980-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-10-19 | 1984-04-19 | 1984-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-10-19 | 1988-04-19 | 1988-10-19 | $7700.00 | Window Closed / Lapsed |