← Back to Patent Explorer
US3697775A Expired / Lapsed US ⏱️ 0.0 years remaining

Three state output logic circuit with bistable inputs

Assignee: Signetics Corp
•
Filing: 1971-04-21
•
Granted: 1972-10-10
•
Expires: 1991-04-21
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A three output state logic circuit includes the last cell of a shift register, which is a flip-flop, coupled to an RS type flipflop which drives a push-pull output circuit. The output circuit is placed in a high impedance or floating logic state by grounding the output terminals of the RS flip-flop. The effect of this grounding is, however, isolated from the last cell of the shift register so that it maintains its stored binary information.

Inventors

  • 👤 James F Kane

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 13:48
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 138 words
A logic circuit comprising: first bistable means having first binary complementary outputs and responsive to an input control signal to switch binary output states; second bistable means having second binary complementary outputs and a pair of inputs coupled to and responsive to a change of state in said first binary outputs to change the states of said second outputs; push pull output means coupled to and driven by said second outputs for providing a binary output in accordance with the states of said second outputs; and means coupled to said second bistable means for temporarily overriding said first outputs and for placing said second outputs in identical binary states, said push pull output means being responsive to said identical states where its output assumes a third floating condition different from said binary output of said push pull means.
Claim 2
Dependent Claim 138 words
A logic circuit comprising: first bistable means having first binary complementary outputs and responsive to an input control signal to switch binary output states; second bistable means having second binary complementary outputs and a pair of inputs coupled to and responsive to a change of state in said first binary outputs to change the states of said second outputs; push pull output means coupled to and driven by said second outputs for providing a binary output in accordance with the states of said second outputs; and means coupled to said second bistable means for temporarily overriding said first outputs and for placing said second outputs in identical binary states, said push pull output means being responsive to said identical states where its output assumes a third floating condition different from said binary output of said push pull means.
Claim 3
Dependent Claim 49 words
A logic circuit as in claim 1 where said second bistable means includes a pair of field effect transistors having input gates coupled to said first outputs whereby said first bistable means is isolated from the effects of said means for placing said second outputs in identical binary states.
Claim 4
Dependent Claim 20 words
A logic circuit as in claim 1 where all of the transistor components of the circuit are field effect transistors.
Claim 5
Dependent Claim 20 words
A logic circuit as in claim 1 where said first bistable means is the last cell of a shift register.
Claim 6
Dependent Claim 29 words
A logic circuit as in claim 1 where said pair of inputs of said second bistable means have a high impedance and drain negligible current from said first outputs.
Claim 7
Dependent Claim 32 words
A logic circuit as in claim 1 where said means for placing said second outputs in identical binary states includes a pair of field effect transistors for selectively concurrently grounding such outputs.

References Cited (Backward Citations)

US3207922A Cited
US3431433A Cited
US3381088A Cited
US3492496A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-10-10 1976-04-10 1976-10-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-10-10 1980-04-10 1980-10-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-10-10 1984-04-10 1984-10-10 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag