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US3840757A Expired / Lapsed US ⏱️ 0.0 years remaining

Flip-flop circuit

Assignee: Hitachi Ltd
•
Filing: 1973-03-27
•
Granted: 1974-10-08
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Expires: 1993-03-27
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Abstract

Abstract A static flip-flop circuit wherein an input terminal and an output terminal of a first inverter circuit are respectively feedback-connected to an output terminal and an input terminal of a second inverter circuit, complementary input signals are respectively applied to an input terminal of either one of the field-effect transistors connected in series between the input terminal of the first inverter circuit and ground and to an input terminal of either one of the field-effect transistors connected in series between said input terminal of the second inverter circuit and ground, the first pulse signal is applied to a fieldeffect transistor connected between an ouptut terminal of said flip-flop circuit and the output terminal of either one of the first and second inverter circuits, and the second pulse signal differing in phase from said first pulse signal is applied to an input electrode of the other of the field-effect transistors connected to the input terminal of the first inverter circuit and to an input electrode of the other of the field-effect transistors connected to the input terminal of the second inverter circuit.

Inventors

  • 👤 K Nomiya
  • 👤 Y Hatsukano

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 20:50
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/35606; G; G11; G11C; G11C19/00; G11C19/28; H03K3/356069; H03K3/356078

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 206 words
A flip-flop circuit comprising a first inverter circuit consisting of a first field-effect transistor in series with a first load, a second inverter circuit consisting of a second field-effect transistor in series with a second load, third and fourth field-effect transistors connected in series between an input terminal of said first inverter circuit and ground, fifth and sixth field-effect transistors connected in series between an input terminal of said second inverter circuit and ground, said input terminals and output terminals of said firsT and second inverter circuits being feedback-connected therebetween, first means for applying complementary first pulse signals respectively to an input electrode of one of said third and fourth fieldeffect transistors and an input electrode of one of said fifth and sixth field-effect transistors, a seventh field-effect transistor connected between an output terminal of said flip-flop circuit and an output terminal of one of said first and second inverter circuits and connected to receive a second pulse as an input, and second means for applying a first pulse signal different in phase from said second pulse signal to an input electrode of the other of said third and fourth field-effect transistors and an input electrode of the other of said fifth and sixth field-effect transistors.
Claim 2
Dependent Claim 206 words
A flip-flop circuit comprising a first inverter circuit consisting of a first field-effect transistor in series with a first load, a second inverter circuit consisting of a second field-effect transistor in series with a second load, third and fourth field-effect transistors connected in series between an input terminal of said first inverter circuit and ground, fifth and sixth field-effect transistors connected in series between an input terminal of said second inverter circuit and ground, said input terminals and output terminals of said firsT and second inverter circuits being feedback-connected therebetween, first means for applying complementary first pulse signals respectively to an input electrode of one of said third and fourth fieldeffect transistors and an input electrode of one of said fifth and sixth field-effect transistors, a seventh field-effect transistor connected between an output terminal of said flip-flop circuit and an output terminal of one of said first and second inverter circuits and connected to receive a second pulse as an input, and second means for applying a first pulse signal different in phase from said second pulse signal to an input electrode of the other of said third and fourth field-effect transistors and an input electrode of the other of said fifth and sixth field-effect transistors.
Claim 3
Dependent Claim 50 words
A flip-flop circuit as defined in claim 1 wherein said first means includes an eighth field-effect transistor connected to the input electrode of said one of said third and fourth field-effect transistors and a source of said first pulse signals connected to the gate electrode of said eighth field-effect transistor.
Claim 4
Dependent Claim 50 words
A flip-flop circuit as defined in claim 1 wherein said first means includes an eighth field-effect transistor connected to the input electrode of said one of said fifth and sixth field-effect transistors and a source of said first pulse signals connected to the gate electrode of said eighth field-effect transistor.
Claim 5
Dependent Claim 23 words
A flip-flop circuit as defined in claim 1 wherein said first and second loads are provided as ninth and tenth field-effect transistors, respectively.
Claim 6
Dependent Claim 20 words
A flip-flop circuit as defined in claim 1 wherein said seventh field-effect transistor is connected to said first inverter circuit.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-10-07 1978-04-08 1978-10-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-10-07 1982-04-08 1982-10-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-10-07 1986-04-08 1986-10-08 $7700.00 Window Closed / Lapsed

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