US4593206A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fixed slew rate bus driver circuit
Assignee: Motorola Solutions Inc
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Filing: 1984-01-16
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Granted: 1986-06-03
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Expires: 2004-01-16
Abstract
Abstract A circuit for driving a serial data bus with serial logic data that is supplied to the circuit while buffering the logic data supplying circuit from the data bus. The circuit provides logic output pulses having controlled slew rates wherein the input logic data is not distorted but which inhibits undesired high frequency components associated with the fast rise and fall times of the leading and trailing edges of the input logic data pulses. The circuit comprises an inverting amplifier having capacitive feedback between the output and the inverting input of the amplifier, a buffer amplifier between the output of the inverting amplifier and the output of the circuit, and current switching circuitry for sinking and sourcing currents of equal magnitude at the input of the inverting amplifier depending on the relative magnitude of the input logic data pulses.
Inventors
- 👤 Robert A. Neidorff
- 👤 W. Eric Main
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:02
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00353
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
163 words
Monolithic driver circuit having an input for driving a load at an output thereof, comprising: inverting amplifier means having an input and an output, said inverting amplifier means providing output signals inverted in phase with respect to input signals applied to said input; current switch means coupled to said input of said inverting amplifier means and being adapted to receive applied logic control signals at said input of the driver circuit for sourcing or sinking currents of substantially equal magnitudes at said input of said inverting amplifier means depending on the phase of said applied logic control signals; feedback means coupled between said output and input of said inverting amplifier means which in conjunction with said inverting amplifier means produces said output signals having controlled and substantially symmetrical slew rates associated therewith; and buffer means coupled between said output of said inverting amplifier means and the output of the driver circuit for buffering said output of said inverting amplifier means from the load.
Claim 2
Dependent Claim
163 words
Monolithic driver circuit having an input for driving a load at an output thereof, comprising: inverting amplifier means having an input and an output, said inverting amplifier means providing output signals inverted in phase with respect to input signals applied to said input; current switch means coupled to said input of said inverting amplifier means and being adapted to receive applied logic control signals at said input of the driver circuit for sourcing or sinking currents of substantially equal magnitudes at said input of said inverting amplifier means depending on the phase of said applied logic control signals; feedback means coupled between said output and input of said inverting amplifier means which in conjunction with said inverting amplifier means produces said output signals having controlled and substantially symmetrical slew rates associated therewith; and buffer means coupled between said output of said inverting amplifier means and the output of the driver circuit for buffering said output of said inverting amplifier means from the load.
Claim 3
Dependent Claim
121 words
The driver circuit of claim 1 wherein said inverting amplifier means includes: a first PNP transistor connected as a common emitter amplifier to said buffer means for producing said inverted output signals at said output of said inverting amplifier means; a second PNP transistor connected as a common collector amplifier and receiving said input signals at said input of said inverting amplifier means; circuit means coupled between said first and second PNP transistors; and current source means for sourcing a current having a predetermined temperature coefficient through said circuit means for biasing said input of said inverting amplifier means at a voltage level the magnitude of which lies midway between the upper and lower magnitudes of said applied logic control signals.
Claim 4
Dependent Claim
120 words
The driver circuit of claim 2 wherein: said first PNP transistor has an emitter, collector, auxiliary collector and base, said emitter being coupled to a first power supply conductor, said collector being coupled to said output of said inverting amplifier means, said base being coupled at a circuit node to both said current source means and said circuit means, said auxiliary collector at least partially surrounding said collector and being connected to said base; and said second PNP transistor has an emitter, collector, and base, said emitter being coupled via said circuit means to said circuit node; said collector being coupled to a second power supply conductor, and said base being coupled to said input of said inverting amplifier means.
Claim 5
Dependent Claim
20 words
The driver of claim 3 wherein: said feedback means is a capacitor; and said circuit means is a first resistor.
Claim 6
Dependent Claim
30 words
The driver of claim 4 wherein said current switch means includes a second resistor connected between an input of the driver circuit and said input of said inverting amplifier means.
Claim 7
Dependent Claim
52 words
The driver of claim 5 wherein said buffer means includes a NPN transistor having an emitter, collector and base, said emitter being coupled to an output of the driver circuit, said collector being coupled to said first power supply conductor, said base being coupled to said output of said inverting amplifier means.
Claim 8
Dependent Claim
71 words
The driver of claim 1 wherein said inverting amplifier means includes: a first PNP transistor connected as a common emitter amplifier for providing said inverted output signals at said output of said inverting amplifier means; a second PNP transistor connected as a common collector amplifier which receives said input signals at said input of said inverting amplifier means; and circuit means coupling said second PNP transistor to said first PNP transistor.
Claim 9
Dependent Claim
56 words
The driver circuit of claim 7 wherein said current switch means is a differential comparator amplifier having first and second inputs and an output, said applied logic control signals being supplied to said first input, said second input receiving a threshold reference voltage and said output being coupled to said input of said inverting amplifier means.
Claim 10
Dependent Claim
32 words
The driver circuit of claim 8 wherein said first PNP transistor includes auxiliary collector means coupled to said circuit means for inhibiting said first PNP transistor from being driven into hard saturation.
Claim 11
Dependent Claim
35 words
The driver circuit of claim 9 wherein said buffer means includes a NPN transistor coupled between said output of said inverting amplifier means and an output of the driver circuit in a voltage follower configuration.
Claim 12
Dependent Claim
13 words
The driver circuit of claim 10 wherein said feedback means is a capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-02 | 1989-12-02 | 1990-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-02 | 1993-12-02 | 1994-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-02 | 1997-12-02 | 1998-06-03 | $7700.00 | Window Closed / Lapsed |