Current limiting output driver

Claim 2

An output driver comprising: a first transistor connected between an output node and a reference voltage terminal and responsive to an input data signal; a second transistor connected between said output node and said reference voltage terminal and responsive to a first feedback signal from said output; and a third transistor connected between said output node and said reference voltage terminal and responsive to a second feedback signal from said output.

Claim 3

The driver of claim 1 further comprising: a first circuit, connected between said output node and a control electrode of said second transistor, for providing said first feedback signal; and a second circuit, connected between said output node and a control electrode of said third transistor, for providing said second feedback signal.

Claim 4

The driver of claim 2 wherein: said first circuit includes a first inverter, a first coincidence gate and second inverter series connected between said output node and the control electrode of said second transistor; and said second circuit includes a third inverter, a second coincidence gate and fourth inverter series connected between said output node and the control electrode of said third transistor.

Claim 5

The driver of claim 3 wherein: said inverters each have an input and an output, said first coincidence gate has a first input connected to the output of said first inverter, a second input connected to an input node for receiving said input data signal, and an output connected to the input of said second inverter; and said second coincidence gate has a first input connected to the output of said third inverter, a second input connected to said input node, and an output connected to the input of said fourth inverter.

Claim 6

The driver of claim 3 wherein said first and second coincidence gates are two-input NAND gates.

Claim 7

The driver of claim 2 wherein said first circuit includes first delaying means for delaying said first feedback signal until after said data signal is provided to said first transistor, and said second circuit includes second delaying means for delaying said second feedback signal until after said first feedback signal is provided to said second transistor.

Claim 8

The driver of claim 6 wherein: said first delaying means includes a first inverter connected between high and low voltage terminals, having an input connected to said output node, and having a first threshold voltage for switching between said high and low voltage terminals; and said second delaying means includes a second inverter connected between said high and low voltage terminals, having an input connected to said output node, and having a second threshold voltage, different than said first threshold voltage, for switching between said high and low voltage terminals.

Claim 9

The driver of claim 7 wherein the threshold voltage of said second inverter is less than the threshold voltage of said first inverter.

Claim 10

The driver of claim 1 wherein said first, second and third transistors are NMOS field effect transistors.

Claim 11

The driver of claim 9 wherein said reference voltage terminal is ground.

Claim 12

The driver of claim 1 further comprising: a pair of inverters series connected between a data supply line and a control electrode of said first transistor for providing said input data signal to said first transistor.

Claim 13

The driver of claim 1 wherein: said first transistor responds to said input data signal by conducting current between said output node and reference voltage terminal with a characteristic first resistance; said second transistor responds to said first feedback signal by conducting current between said output node and reference voltage terminal with a characteristic second resistance; said third transistor responds to said second feedback signal by conducting current between said output node and reference voltage terminal with a characteristic third resistance; and said first resistance is greater than said second resistance and said second resistance is greater than said third resistance.

Claim 14

The driver of claim 12 wherein said first, second and third transistors are MOS field effect transistors.

Claim 15

The driver of claim 13 wherein the channel width of said first transistor is less than the channel width of said second transistor and the channel width of said second transistor is less than the channel width of said third transistor.

Claim 16

The driver of claim 14 wherein the channel width of said second transistor is generally twice the channel width of said first transistor and the channel width of said third transistor is generally three to four times the channel width of said first transistor.

Claim 17

The driver of claim 2 further comprising means for reducing current spikes in said output node in response to said input data signal.

Claim 18

The driver of claim 16 wherein: said first circuit includes a first inverter connected to said output node, and said second circuit includes a second inverter connected to said output node; and said means includes said first, second and third transistors characterized by the characteristic resistance of said transistors, and includes said first and second inverters characterized by the threshold voltages of said inverters.

Claim 19

The driver of claim 17 wherein: the characteristic resistance of said first transistor is greater than the characteristic resistance of said second transistor and the characteristic resistance of said second transistor is greater than the characteristic resistance of said third transistor; and the threshold voltage of said second inverter is less than the threshold voltage of said first inverter.

Claim 20

An output driver for reducing current spikes in said output comprising: a first transistor connected between an output node and a reference voltage terminal and responsive to an input data signal for conducting current therebetween with a characteristic first resistance; a second transistor connected between said output node and said reference voltage terminal and responsive to a first feedback signal from said output for conducting current between said output node and reference voltage terminal with a characteristic second resistance; a third transistor connected between said output node and said reference voltage terminal and responsive to a second feedback signal from said output for conducting current between said output node and reference voltage terminal with a characteristic third resistance, wherein said first resistance is greater than said second resistance and said second resistance is greater than said third resistance; a first circuit, connected between said output node and a control electrode of said second transistor, for providing said first feedback signal, wherein said first circuit includes first delaying means for delaying said first feedback signal until after said data signal is provided to said first transistor; and a second circuit, connected between said output node and a control electrode of said third transistor, for providing said second feedback signal, wherein said second circuit includes second delaying means for delaying said second feedback signal until after said first feedback signal is provided to said second transistor.

Claim 21

An output driver for reducing current spikes in said output comprising: a first transistor connected between an output node and a reference voltage terminal and responsive to an input data signal for conducting current therebetween with a characteristic first resistance; a second transistor connected between said output node and said reference voltage terminal and responsive to a first feedback signal from said output for conducting current between said output node and reference voltage terminal with a characteristic second resistance; a third transistor connected between said output node and said reference voltage terminal and responsive to a second feedback signal from said output for conducting current between said output node and reference voltage terminal with a characteristic third resistance, wherein said first resistance is greater than said second resistance and said second resistance is greater than said third resistance; a first circuit, connected between said output node and a control electrode of said second transistor, for providing said first feedback signal, wherein said first circuit includes first delaying means for delaying said first feedback signal until after said data signal is provided to said first transistor; and a second circuit, connected between said output node and a control electrode of said third transistor, for providing said second feedback signal, wherein said second circuit includes second delaying means for delaying said second feedback signal until after said first feedback signal is provided to said second transistor.

Claim 22

The driver of claim 19 wherein: said first circuit includes a first inverter, a first coincidence gate and second inverter series connected between said output node and the control electrode of said second transistor; and said second circuit includes a third inverter, a second coincidence gate and fourth inverter series connected between said output node and a control electrode of said third transistor.

Claim 23

The driver of claim 20 wherein: said first, second and third transistors are MOS field effect transistors; and the channel width of said first transistor is less than the channel width of said second transistor and the channel width of said second transistor is less than the channel width of said third transistor.

Claim 24

The driver of claim 21 wherein: said first delaying means includes said first inverter connected between high and low voltage terminals, having an input connected to said output node, and having a first threshold voltage for switching between said high and low voltage terminals; said second delaying means includes said third inverter connected between said high and low voltage terminals, having an input connected to said output node, and having a second threshold voltage for switching between said high and low voltage terminals; and the threshold voltage of said second inverter is less than the threshold voltage of said first inverter.

Claim 25

The driver of claim 22 wherein: said inverters each have an input and an output, said first coincidence gate is a two-input NAND gate having a first input connected to the output of said first inverter, a second input connected to an input node for receiving said input data signal, and an output connected to the input of said second inverter; and said second coincidence gate is a two-input NAND gate having a first input connected to the output of said third inverter, a second input connected to said input node, and an output connected to the input of said fourth inverter.

Claim 26

The driver of claim 23 wherein said first, second and third transistors are NMOS field effect transistors, and wherein said reference voltage and low voltage terminals are ground.

Claim 27

The driver of claim 24 further comprising: a pair of inverters series connected between a data supply line and said first transistor for providing said input data signal to said first transistor.