Output buffer with di/dt and dv/dt and tri-state control

Claim 2

An output buffer comprising: a voltage supply line for providing a desired voltage level; drive control circuitry coupled to the voltage supply line for generating a control signal on a control signal node responsive to an input; output circuitry for pulling an output node towards said voltage level responsive to said control signal; current transient control circuitry coupled to said drive control circuitry for detecting a voltage spike on said voltage supply line and varying the control signal responsive thereto; and edge and rate control circuitry coupled to said drive control circuitry for varying said control signal such that said output signal has a controlled edge rate during a voltage transition on said output node.

Claim 3

The output buffer of claim 1, wherein drive control circuitry comprises a transistor connected between the voltage supply line and the control signal node responsive to said input.

Claim 4

The output buffer of claim 2, wherein said transistor comprises a first transistor and wherein said current transient control circuitry comprises a second transistor enabled by a voltage transient on said voltage supply line and operable to drive said first transistor to adjust said control signal in response to said voltage transient.

Claim 5

The output buffer of claim 3, wherein said first transistor comprises a p channel transistor having a source coupled to said voltage supply line and a drain coupled to said control signal node.

Claim 6

The output buffer of claim 1, wherein said voltage level is a positive voltage level and said second transistor comprises a p channel transistor having a gate coupled to said voltage supply line, a source coupled to a second voltage supply line, and a drain coupled to the gate of said first transistor.

Claim 7

An output buffer comprising: a voltage supply line for providing a desired voltage level; drive control circuitry coupled to the voltage supply for generating a control signal on a control signal node responsive to an input; output circuitry for pulling an output node towards said voltage level responsive to said control signal; and edge rate control circuitry coupled to said drive control circuitry and to the output node for varying said control signal such that said output signal has a controlled edge rate during a voltage transition on said output node.

Claim 8

An output buffer comprising: a voltage supply line for providing a desired voltage level; drive control circuitry coupled to the voltage supply for generating a control signal on a control signal node responsive to an input; output circuitry for pulling an output node towards said voltage level responsive to said control signal; and edge rate control circuitry coupled to said drive control circuitry and to the output node for varying said control signal such that said output signal has a controlled edge rate during a voltage transition on said output node.

Claim 9

The output buffer of claim 6, wherein said edge rate control circuitry comprises: a capacitor coupling said drive control circuitry with said output node for controlling the voltage transition of said output signal as a function of a current provided to said capacitor; and circuitry for selectively providing said current as a function of a reference voltage.

Claim 10

The output buffer of claim 7, wherein said circuitry for selectively providing said current comprises a first transistor for setting said current as a function of said reference voltage and a second transistor for switching said current to said capacitor.

Claim 11

The output buffer of claim 8, wherein said drive control circuitry comprises a transistor connected between the voltage supply line and the control signal node responsive to said input.

Claim 12

An output buffer comprising: a tri-state enable input terminal; a data input terminal; a first voltage supply line; a second voltage supply line; a first ground line; a second ground line; input logic circuitry having a first input coupled to said tri-state enable terminal and a second input coupled to said data input terminal; low to high drive control circuitry coupled to said input logic circuitry; high to low drive control circuitry coupled to said input logic circuitry; low to high voltage transition sense circuitry coupled to a low to high reference voltage, said output terminal and said low to high drive control circuitry; high to low voltage transition sense circuitry coupled to a high to low reference voltage said output terminal and an output coupled to said high to low drive control circuitry; low to high current transition sense circuitry coupled to said first voltage supply voltage line, to a second supply voltage line and said low to high drive control circuitry; high to low current transition sense circuitry coupled to said first ground line, said second ground line and said high to low drive control circuitry; upper output drive circuitry coupled to said low to high drive control circuitry, said second supply voltage line and said output terminal; and lower output drive circuitry coupled to said high to low drive control circuitry, said second ground line and said output terminal.

Claim 13

An output buffer comprising: a tri-state enable input terminal; a data input terminal; a first voltage supply line; a second voltage supply line; a first ground line; a second ground line; input logic circuitry having a first input coupled to said tri-state enable terminal and a second input coupled to said data input terminal; low to high drive control circuitry coupled to said input logic circuitry; high to low drive control circuitry coupled to said input logic circuitry; low to high voltage transition sense circuitry coupled to a low to high reference voltage, said output terminal and said low to high drive control circuitry; high to low voltage transition sense circuitry coupled to a high to low reference voltage said output terminal and an output coupled to said high to low drive control circuitry; low to high current transition sense circuitry coupled to said first voltage supply voltage line, to a second supply voltage line and said low to high drive control circuitry; high to low current transition sense circuitry coupled to said first ground line, said second ground line and said high to low drive control circuitry; upper output drive circuitry coupled to said low to high drive control circuitry, said second supply voltage line and said output terminal; and lower output drive circuitry coupled to said high to low drive control circuitry, said second ground line and said output terminal.

Claim 14

The output buffer of claim 10 wherein said upper output drive circuitry comprises: a bipolar transistor having a collector coupled to said second supply voltage line, a base coupled to low to high drive control circuitry and an emitter coupled to said output terminal; and a field effect transistor having one of its source or drain coupled to said second supply voltage line, a gate coupled to low to high drive control circuitry and another one of its source or drain coupled to said output terminal.

Claim 15

The output buffer of claim 11, wherein said lower output drive circuitry comprises: a bipolar transistor having a collector coupled to said output terminal, a base coupled to said high to low drive control circuitry and an emitter coupled to said second ground line; and a field effect transistor having one of its source or drain coupled to said output terminal, a gate coupled to said high to low drive control circuitry and another one of its source or drain coupled to said second ground line.

Claim 16

The output buffer of claim 12, wherein said high to low drive control circuitry includes a high to low drive field effect transistor having one of its source or drain coupled to said output terminal, a gate coupled to said input logic circuitry and another one of its source or drain coupled to said base of said bipolar transistor of said lower output drive circuitry.

Claim 17

The output buffer of claim 13, wherein said high to low current transition sense circuitry comprises a sensing field effect transistor having one of its source or drain coupled to said gate of said drive field effect transistor, a gate coupled to said drive field effect transistor, a gate coupled to said second ground line and another one of its source or drain region coupled to said first ground line.

Claim 18

The output buffer of claim 11, wherein said low to high drive control circuitry includes a low to high drive field effect transistor having one of its source or drain coupled to said second supply voltage line, a gate coupled to said input logic circuitry and another one of its source or drain coupled to said base of said bipolar transistor of said upper output drive circuitry.

Claim 19

The output buffer of claim 15, wherein said low to high current transition sense circuitry comprises a sensing field effect transistor having one of its source or drain coupled to said first supply voltage line, a gate coupled to said second supply voltage line and another one of its source or drain coupled to said base of said drive field effect transistor.

Claim 20

The output buffer of claim 10, wherein said high to low voltage transition circuitry comprises: a current setting field effect transistor having one of its source or drain coupled to said second supply voltage line and a gate coupled to a said high to low reference voltage; a gating field effect transistor having one of its source or drain coupled to another one of the source or drain of said current setting transistor, and a gate coupled to said input logic circuitry; and a capacitor having a first plate coupled to another one of the source or drain of said gating transistor and a second plate coupled to said output terminal.

Claim 21

The output buffer of claim 10, wherein said low to high voltage transition sense circuitry comprises: a current setting field effect transistor having one of its source or drain coupled to said second ground line and a gate coupled to said low to high reference voltage; a gating field effect transistor having one of its source or drain coupled to another one of the source or drain of said current setting transistor and a gate coupled to said logic input circuitry; and a capacitor having a first plate coupled to the other one of the source or drain of said gating transistor and a second plate coupled to said output terminal.

Claim 22

The output buffer of claim 17, and further comprising high to low transition speed up circuitry including: a first speed-up field effect transistor having one of its source or drain switchably coupled to said second voltage supply line through said input logic circuitry and another one of its source or drain coupled to said gate of said high to low drive field effect transistor; a second speed-up field effect transistor having one of its source or drain coupled to said gate of said second supply voltage line, a gate coupled to said input logic circuitry and another one of its source or drain coupled to a gate of said first speed up field effect transistor; and a shut-off field effect transistor having one of its source or drain coupled to a gate of said first speed up transistor, a gate coupled to said gate of said high to low drive field effect transistor and another one of its source or drain coupled to said second ground line.

Claim 23

The output buffer of claim 18, and further comprising low to high transition speed up circuitry including: a first speed-up field effect transistor having one of its source or drain switchably coupled to said second groundline through said input logic circuitry and another one of its source or drain coupled to said gate of said low to high drive field effect transistor; a second speed-up field effect transistor having one of its source or drain coupled to a gate of said first speed up transistor, a gate coupled to said input logic circuitry and another one of its source or drain coupled to said second ground; and a shut-off field effect transistor having one of its source or drain coupled to said second voltage supply line, a gate coupled to said another one of the source or drain of said first speed up transistor and said gate of said low to high drive transistor and another one of its source or drain coupled to said gate of said first speed up transistor.

Claim 24

An output buffer comprising: a first voltage supply line for providing a first desired voltage level; a second voltage supply line for providing a second desired voltage level; first drive control circuitry coupled to the first voltage supply for generating a first control signal on a first control signal node responsive to a first input; second drive control circuitry for generating a second control signal on a second control signal node responsive to a second input; first output circuitry for pulling an output node towards said first desired voltage level responsive to said first control signal; second output circuitry for pulling said output node towards said second voltage level responsive to said second control signal; first transient control circuitry coupled to said first drive control circuitry for detecting a voltage spike on said first voltage supply line and varying the first control signal responsive thereto; second current transient control circuitry coupled to said second drive control circuitry for detecting a voltage spike on said second supply line and varying the second control signal responsive thereto; first edge rate control circuitry coupled to said first drive control circuitry for varying said first control signal such that said output signal has a controlled edge rate during a voltage transition on said output node towards said first voltage level; and second edge rate control circuitry coupled to said second drive control circuitry for varying said second control signal such that said output signal has a controlled edge rate during a voltage transition on said output node towards said second voltage level.

Claim 25

An output buffer comprising: a first voltage supply line for providing a first desired voltage level; a second voltage supply line for providing a second desired voltage level; first drive control circuitry coupled to the first voltage supply for generating a first control signal on a first control signal node responsive to a first input; second drive control circuitry for generating a second control signal on a second control signal node responsive to a second input; first output circuitry for pulling an output node towards said first desired voltage level responsive to said first control signal; second output circuitry for pulling said output node towards said second voltage level responsive to said second control signal; first transient control circuitry coupled to said first drive control circuitry for detecting a voltage spike on said first voltage supply line and varying the first control signal responsive thereto; second current transient control circuitry coupled to said second drive control circuitry for detecting a voltage spike on said second supply line and varying the second control signal responsive thereto; first edge rate control circuitry coupled to said first drive control circuitry for varying said first control signal such that said output signal has a controlled edge rate during a voltage transition on said output node towards said first voltage level; and second edge rate control circuitry coupled to said second drive control circuitry for varying said second control signal such that said output signal has a controlled edge rate during a voltage transition on said output node towards said second voltage level.

Claim 28

The method of claim 22, wherein said step of detecting a voltage spike on the voltage supply line comprises the step of enabling a transistor responsive to a voltage transient on the voltage supply line to vary the control signal.

Claim 29

The method of claim 23, wherein said step of varying the control signal such that the output signal has a controlled edge comprises the steps of: charging a capacitor to control the voltage transition of the output signal as a function of current provided to the capacitor; and selectively providing current to the capacitor as a function of a reference voltage.