Noise reduction for output drivers

Claim 2

A logic driver for compensating for the effects of parasitic inductance comprising: means for receiving a logic signal of one current level; means for generating an output current at another current level; control logic means connected between said receiving means and said current generating means and adapted to change the output current in accordance with the received logic signal; voltage altering means connected between a potential source and said means for receiving a logic signal and between said potential source and said means for generating an output current, for altering the effects of a voltage produced by parasitic inductance.

Claim 3

The driver of claim 1 wherein the voltage altering means comprises a resistance.

Claim 4

The driver of claim 1 wherein the voltage altering means comprises a controlled resistance adapted to change its resistance in accordance with the voltage produced by the parasitic inductance.

Claim 5

The driver of claim 3 wherein the controlled resistance comprises a transistor.

Claim 6

The driver of claim 4 wherein the transistor is operable at a predetermined voltage produced by said parasitic inductance to increase the resistance connected to said inductance.

Claim 7

The driver of claim 1 wherein the voltage altering means comprises a fixed resistance and a voltage variable resistance.

Claim 8

The driver of claim 6 wherein the voltage variable resistance comprises a transistor.

Claim 9

The driver of claim 7 wherein the transistor changes its resistance in accordance with a predetermined voltage produced by the parasitic inductance.

Claim 10

An output driver for compensating for the effects of inherent inductance comprising: means for receiving an input signal comprising a series of alternate high and low logic levels, a pair of drivers connected to a supply potential, one for driving an output load at one current level in response to said high signals, the other for driving an output load at another current level in response to said low signals, control logic means for directing said high input signals to said high output driver and for directing said low output signals to said low output driver, means connected between said supply potential and said output drivers for increasing the resistance of said drivers and thereby reducing the rate of increased voltage by said inherent inductance.

Claim 11

An output driver for compensating for the effects of inherent inductance comprising: means for receiving an input signal comprising a series of alternate high and low logic levels, a pair of drivers connected to a supply potential, one for driving an output load at one current level in response to said high signals, the other for driving an output load at another current level in response to said low signals, control logic means for directing said high input signals to said high output driver and for directing said low output signals to said low output driver, means connected between said supply potential and said output drivers for increasing the resistance of said drivers and thereby reducing the rate of increased voltage by said inherent inductance.

Claim 12

The invention of claim 9 wherein the means connected between said supply potential and said output drivers is a fixed resistance.

Claim 13

The invention of claim 10 wherein the means connected between said supply potential and said output drivers is a variable resistance.

Claim 14

The invention of claim 9 wherein the means connected between said supply potential and said output drivers includes a fixed and a variable resistance.

Claim 15

The invention of claim 9 wherein the output drivers comprise a pair of transistors, each having a control electrode for controlling the resistance of the transistor to the passage of current through said transistor in accordance with the voltage on said control electrode and the means connected between said supply potential and said drivers comprises a further pair of transistors.

Claim 16

The invention of claim 13 wherein each of the further pair of transistors comprises a control electrode coupled to the voltage generated by said inductance and a further electrode connected to the control electrode of one of the drivers for reducing the voltage on the control electrode of the driver when the voltage generated by the inductance exceeds a predetermined level.

Claim 19

The method of claim 15 wherein the step of reducing further comprises selectively varying a resistance to the parasitic inductance.

Claim 20

The method of claim 16 wherein the step of selectively increasing the resistance comprises momentarily interrupting said generating.

Claim 21

A control circuit for preventing excessive power signal variation due to parasitic inductance associated with an output transistor whose conduction path is connected in series across a power supply potential and an output terminal, comprising: control logic means coupled to said power supply potential and said output transistor and adapted to change an output of said output transistor in accordance with a received logic signal; isolation means for providing isolation between a first potential supply node in said output transistor conduction path and a second potential supply node to said control logic means; and sensing means for sensing potential differences between said first and second power supply nodes and operatively coupled for momentarily turning off said output transistor in response to a desired potential difference.

Claim 22

A control circuit for preventing excessive power signal variation due to parasitic inductance associated with an output transistor whose conduction path is connected in series across a power supply potential and an output terminal, comprising: control logic means coupled to said power supply potential and said output transistor and adapted to change an output of said output transistor in accordance with a received logic signal; isolation means for providing isolation between a first potential supply node in said output transistor conduction path and a second potential supply node to said control logic means; and sensing means for sensing potential differences between said first and second power supply nodes and operatively coupled for momentarily turning off said output transistor in response to a desired potential difference.

Claim 23

The control circuit of claim 18 wherein said parasitic inductance is disposed in series with said first potential supply node and said power supply potential, and in series with said power supply potential and said second potential supply node.

Claim 24

The control circuit of claim 18, further comprising: means for preventing turning on of said output transistor until said sensing means ceases turning off said output transistor.

Claim 25

The control circuit of claim 18 wherein said isolation means comprises first resistance means disposed between said power supply potential and said first power supply node and second resistance means disposed between said power supply potential and said second power supply node.

Claim 26

The control circuit of claim 18 wherein, said control logic means comprises a NAND gate, said sensing means comprises a transistor, said isolation means comprises first resistance means disposed between said power supply potential and said first potential supply node and second resistance means disposed between said power supply potential and said second potential supply node.

Claim 27

The control circuit of claim 22 wherein said NAND gate is composed of a plurality of active devices and at least one resistive element disposed in a discharge path of said output transistor such to prevent turning on of said output transistor until said sensing means ceases turning off said output transistor.

Claim 28

An output driver control circuit, comprising: an output stage including a first drive transistor for clamping the output at a first output level, and a second drive transistor for clamping the output at a second output level; a first control logic means coupled to a power supply potential and said first drive transistor and adapted to change the output of said first drive transistor in accordance with a received logic signal; second control logic means coupled to said power supply potential and said second drive transistor and adapted to change an output of said second transistor in accordance with a received logic signal; isolation means for isolating a first potential supply node of said first drive transistor from a second potential supply node of said first control means and for isolating a third potential supply node of said second drive transistor from a forth potential supply node of said second control means; first sensing means for sensing potential differences between said first and second potential supply nodes; second sensing means for sensing potential differences between said third and forth potential supply nodes; said first and second sensing means operatively coupled for respectively turning off said respective first and second drive transistors in response to desired potential differences.

Claim 29

An output driver control circuit, comprising: an output stage including a first drive transistor for clamping the output at a first output level, and a second drive transistor for clamping the output at a second output level; a first control logic means coupled to a power supply potential and said first drive transistor and adapted to change the output of said first drive transistor in accordance with a received logic signal; second control logic means coupled to said power supply potential and said second drive transistor and adapted to change an output of said second transistor in accordance with a received logic signal; isolation means for isolating a first potential supply node of said first drive transistor from a second potential supply node of said first control means and for isolating a third potential supply node of said second drive transistor from a forth potential supply node of said second control means; first sensing means for sensing potential differences between said first and second potential supply nodes; second sensing means for sensing potential differences between said third and forth potential supply nodes; said first and second sensing means operatively coupled for respectively turning off said respective first and second drive transistors in response to desired potential differences.

Claim 30

The output driver control circuit of claim 24 wherein said first control logic means comprises a NAND gate, said second control logic means comprises a NOR gate, said first and second sensing means comprise first and second transistors, said first and second isolation means comprise first and second resistance means.

Claim 31

The output driver control circuit of claim 25 further, comprising: first means for preventing turning on of said first drive transistor until said first sensing means ceases turning off said first output transistor; and second means for preventing turning on of said second drive transistor until said second sensing means ceases turning off said second output transistor.