Threshold controlled input circuit for an integrated circuit

Claim 2

A binary circuit comprising: a first series summing amplifier including a first p-channel FET, a second p-channel, FET, a first n-channel FET, and a second n-channel FET; wherein the first p-channel FET, the second p-channel FET, the first n-channel FET, and the second n-channel FET are connected in series; wherein a gate of the first p-channel FET is coupled to a gate of the first n-channel FET to provide a first inverting input; wherein a gate of the second p-channel FET is coupled to a gate of the second n-channel FET to provide a second inverting input; wherein the output node of said first series summing amplifier is located at the series connection point between said second p-channel FET and said second n-channel FET; wherein the output node of said first series summing amplidfier provides a binary output voltage that is a logic low if an input voltage on said first inverting input exceeds an input voltage on said second inverting input by a threshold voltage, otherwise said binary output is a logic high; and first means for providing a first reference voltage connected to said first inverting input including a second series summing amplifier having a first inverting input, a second inverting input and an output; a first complementary series inverter stage having an input and an output; and a second complementary series inverter stage having an input and an output; wherein said second series summing amplifier is connected between V DD and circuit ground; wherein said input of the first complementary inverter stage is connected to said output of said second series summing amplifier; and wherein said input of said second complementary series inverter stage is connected to said output of said first complementary series inverter stage; wherein said first inverting input is connected to a second reference voltage; wherein said second inverting input is connected to said output of said second complementary series inverter; and wherein an output voltage at the output of said second complementary series inverter stage is said first reference voltage.

Claim 3

A binary circuit as set forth in claim 1, further comprising: a third series summing amplifier including a first p-channel FET, a second p-channel FET, a first n-channel FET, and a second n-channel FET; wherein the first p-channel FET, the second p-channel FET, the first n-channel FET, and the second n-channel FET are connected in series; wherein a gate of the first p-channel FET is coupled to a gate of the first n-channel FET to provide a first inverting input; wherein a gate of the second p-channel FET is coupled to a gate of the second n-channel FET to provide a second inverting input; wherein the output node of said third series summing amplifier is located at the series connection point between said second p-channel FET and said second n-channel FET; wherein the output node of said third series summing amplidfier provides a binary output voltage that is a logic low if an input voltage on said first inverting input exceeds an input voltage on said second inverting input by a threshold voltage, otherwise said binary output is a logic high; and wherein said means for providing a reference voltage is connected to said first inverting input of said third series summing amplifier.

Claim 4

A binary circuit as set forth in claim 1, further comprising: a third series summing amplifier including a first p-channel FET, a second p-channel FET, a first n-channel FET, and a second n-channel FET; wherein the first p-channel FET, the second p-channel FET, the first n-channel FET and the second n-channel FET are connected in series; wherein a gate of the first p-channel FET is coupled to a gate of the first n-channel FET to provide a first inverting input; wherein a gate of the second p-channel FET is coupled to a gage of the second n-channel FET to provide a second inverting input; wherein the output node of said third series summing amplifier is located at the series connection point between said second p-channel FET and said second n-channel FET; wherein the output node of said third series summing amplidfier provides a binary output voltage that is a logic low if an input voltage on said first inverting input exceeds an input voltage on said second inverting input by a threshold voltage, otherwise said binary output is a logic high; wherein said means for providing a reference voltage is connected to said first inverting input of said third series summing amplifier; means for providing a binary complement of a logic level impressed upon an input of said providing means at an output of said providing means, said providing means including a single input connected to said output of said first series summing amplifier; and a SET-RESET flip-flop having its SET input connected to said output of said providing means and its RESET input connected to said output of said third series summing amplifier; wherein said second inverting input of said first series summing amplifier is connected to said second inverting input of said third series summing amplifier and to an input terminal; and wherein circuitry comprising a Schmitt trigger is formed from said input terminal to an output of said SET-RESET flip-flop.

Claim 5

A binary circuit as set forth in claim 1, further comprising: a third series summing amplifier including a first p-channel FET, a second p-channel FET, a first n-channel FET, and a second n-channel FET; wherein the first p-channel FET, the second p-channel FET, the first n-channel FET and the second n-channel FET are connected in series; wherein a gate of the first p-channel FET is coupled to a gate of the first n-channel FET to provide a first inverting input; wherein a gate of the second p-channel FET is coupled to a gate of the second n-channel FET to provide a second inverting input; wherein the output node of said third series summing amplifier is located at the series connection point between said second p-channel FET and said second n-channel FET; wherein the output node of said first series summing amplidfier provides a binary output voltage that is a logic low if an input voltage on said first inverting input exceeds an input voltage on said second inverting input by a threshold voltage, otherwise said binary output is a logic high; second means for providing a reference voltage which is connected to said first inverting input of said third series summing amplifier; means for providing a binary complement of a logic level impressed upon an input of said providing means at an output of said providing means, said providing means including a single input connected to said output of said first series summing amplifier means; and a SET-RESET flip-flop having its SET input connected to said output of said providing means and its RESET input connected to said output of said third series summing amplifier; wherein said second inverting input of said first series summing amplifier is connected to said second inverting input of said third series summing amplifier and to an input terminal; and wherein circuitry comprising a Schmitt trigger is formed from said input terminal to an output of said SET-RESET flip-flop.

Claim 6

A binary circuit as set forth in claim 1 wherein said second reference voltage is provided by a voltage divider.

Claim 7

A binary circuit as set forth in claim 5 wherein said first complementary series inverter includes a p-channel FET connected in series with an n-channel FET.

Claim 8

A binary circuit as set forth in claim 6, wherein said second complementary series inverter includes a p-channel FET connected in series with an n-channel FET.

Claim 9

A binary integrated circuit comprising: a voltage reference means for providing a highly accurate, highly stable first reference voltage; a plurality of input pads for receiving external binary signals; a plurality of input circuits, each substantially the same as the rest of the plurality of input circuits; and each of said plurality of input circuits having a data input connected to a respective input pad of said plurality of input pads and a threshold control voltage input connected to said voltage reference means; each of said plurality of input circuits including a series summing amplifier including a first p-channel FET, a second p-channel FET, a first n-channel FET, and a second n-channel FET; wherein the first p-channel FET, the second p-channel FET, the first n-channel FET, and the second n-channel FET are connected in series; wherein a gate of the first p-channel FET is coupled to a gate of the first n-channel FET to provide a first inverting input which is the threshold control voltage input; wherein a gate of the second p-channel FET is coupled to a gate of the second n-channel FET to provide a second inverting input which is the data input; wherein the output node of said series summing amplifier is located at the series connection point between said second p-channel FET and said second n-channel FET; wherein the output node of said series summing amplidfier provides a binary output voltage that is a logic low if an input voltage on said threshold control voltage input exceeds an input voltage on said data input by a threshold voltage, otherwise said binary output is a logic high; wherein said reference voltage controls the threshold voltage and includes another series summing amplifier having a first inverting input, a second inverting input and an output; a first complementary series inverter stage having an input and an output; and a second complementary series inverter stage having an input and an output; wherein said other series summing amplifier is connected between V DD and circuit ground; wherein said input of the first complementary inverter stage is connected to said output of said other series summing amplifier; and wherein said input of the first complementary series inverter stage is connected to said output of said first complementary series inverter stage; wherein said first inverting input is connected to a second reference voltage; wherein said second inverting input is connected to said output of said second complementary series inverter; and wherein an output voltage at the output of said second complementary series inverter stage is said first reference voltage.

Claim 10

A binary integrated circuit comprising: a voltage reference means for providing a highly accurate, highly stable first reference voltage; a plurality of input pads for receiving external binary signals; a plurality of input circuits, each substantially the same as the rest of the plurality of input circuits; and each of said plurality of input circuits having a data input connected to a respective input pad of said plurality of input pads and a threshold control voltage input connected to said voltage reference means; each of said plurality of input circuits including a series summing amplifier including a first p-channel FET, a second p-channel FET, a first n-channel FET, and a second n-channel FET; wherein the first p-channel FET, the second p-channel FET, the first n-channel FET, and the second n-channel FET are connected in series; wherein a gate of the first p-channel FET is coupled to a gate of the first n-channel FET to provide a first inverting input which is the threshold control voltage input; wherein a gate of the second p-channel FET is coupled to a gate of the second n-channel FET to provide a second inverting input which is the data input; wherein the output node of said series summing amplifier is located at the series connection point between said second p-channel FET and said second n-channel FET; wherein the output node of said series summing amplidfier provides a binary output voltage that is a logic low if an input voltage on said threshold control voltage input exceeds an input voltage on said data input by a threshold voltage, otherwise said binary output is a logic high; wherein said reference voltage controls the threshold voltage and includes another series summing amplifier having a first inverting input, a second inverting input and an output; a first complementary series inverter stage having an input and an output; and a second complementary series inverter stage having an input and an output; wherein said other series summing amplifier is connected between V DD and circuit ground; wherein said input of the first complementary inverter stage is connected to said output of said other series summing amplifier; and wherein said input of the first complementary series inverter stage is connected to said output of said first complementary series inverter stage; wherein said first inverting input is connected to a second reference voltage; wherein said second inverting input is connected to said output of said second complementary series inverter; and wherein an output voltage at the output of said second complementary series inverter stage is said first reference voltage.

Claim 11

A binary integrated circuit as set forth in claim 8 wherein said second reference voltage is provided by a voltage divider.

Claim 12

A binary integrated circuit as set forth in claim 9 wherein said first complementary series inverter includes a p-channel FET connected in series with an n-channel FET.

Claim 13

A binary integrated circuit as set forth in claim 10 wherein said second complementary series inverter includes a p-channel FET connected in series with an n-channel FET.