US4358689A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog to digital interface circuit
Assignee: Motorola Solutions Inc
•
Filing: 1980-07-07
•
Granted: 1982-11-09
•
Expires: 2000-07-07
Abstract
Abstract An interface circuit adapted to receive an analog input signal for generating first and second output signals at respective outputs in response to the input signal varying above a first reference voltage level and varying below a second reference voltage level. The interface circuit comprising first and second circuits each of which has an input coupled to the input of the interface circuit and receiving the first and second reference voltage levels respectively. Each one of the two circuits includes a voltage translation circuit for translating the reference voltage level supplied thereto and a comparator to produce the particular output signal in response to the input signal level assuming the aforementioned relationship with respect to the respective two reference voltage levels.
Inventors
- 👤 Robert B. Jarrett
- 👤 James J. LoCascio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:50
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/08
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
175 words
An interface circuit for providing first and second output signals in response to an applied input signal, the magnitude of which may vary above and below first and second reference voltage levels, comprising: first circuit means having first and second inputs and an output which is responsive to the magnitude of the input signal that is supplied to said first input becoming substantially equal to the first voltage reference level that is supplied at said second input for both clamping said magnitude at the first voltage reference level to inhibit further increases in said magnitude thereof and providing the first output signal at said output; second circuit means having first and second inputs and an output which is responsive to the magnitude of the input signal that is supplied to said first input becoming substantially equal to the second reference level that is supplied to said second input for both clamping said magnitude at the second reference level to inhibit further decrease in said magnitude thereof and providing the second output signal at said output.
Claim 2
Dependent Claim
175 words
An interface circuit for providing first and second output signals in response to an applied input signal, the magnitude of which may vary above and below first and second reference voltage levels, comprising: first circuit means having first and second inputs and an output which is responsive to the magnitude of the input signal that is supplied to said first input becoming substantially equal to the first voltage reference level that is supplied at said second input for both clamping said magnitude at the first voltage reference level to inhibit further increases in said magnitude thereof and providing the first output signal at said output; second circuit means having first and second inputs and an output which is responsive to the magnitude of the input signal that is supplied to said first input becoming substantially equal to the second reference level that is supplied to said second input for both clamping said magnitude at the second reference level to inhibit further decrease in said magnitude thereof and providing the second output signal at said output.
Claim 3
Dependent Claim
75 words
The interface circuit of claim 1 wherein said first circuit means includes: first voltage translation means for translating said first reference voltage level downward to a third reference voltage level; and comparator means for comparing said magnitude of the applied input signal to said third reference voltage level for producing the first output signal at said output of said first circuit means when the input signal becomes substantially equal to said third reference voltage level.
Claim 4
Dependent Claim
71 words
The interface circuit of claim 2 wherein said first voltage translation means being a first transistor of a first conductivity type having a base, emitter and collector, said base being adapted to receive said first voltage reference level, said emitter being coupled to a terminal at which is provided a ground reference potential, said collector being coupled to a power supply conductor at which is supplied a source of operating potential.
Claim 5
Dependent Claim
65 words
The interface circuit of claim 3 wherein said comparator means being a second transistor of a second conductivity type having a base, an emitter, and a first collector, said base being coupled to said emitter of said first transistor, said emitter being coupled to said first input of said first circuit means, said first collector being coupled to said output of said first circuit means.
Claim 6
Dependent Claim
26 words
The interface circuit of claim 4 wherein said second transistor includes a second collector coupled to said terminal at which is supplied said ground reference potential.
Claim 7
Dependent Claim
65 words
The interface circuit of claim 5 wherein said second circuit means includes: second voltage translation means adapted to receive said second reference voltage level for translating the same to a fourth reference voltage level; and comparator means for comparing the magnitude of the input signal to said fourth reference voltage level for providing the second output signal at the output of said second circuit means.
Claim 8
Dependent Claim
62 words
The interface circuit of claim 6 wherein said second voltage translation means includes a third transistor of said second conductivity type having a base, emitter, and collector, said base being said second input of said second circuit means, said collector being coupled to said terminal at which is supplied said ground reference potential and said emitter being coupled to a current source.
Claim 9
Dependent Claim
68 words
The interface circuit of claim 7 wherein said comparator means of said second circuit means includes a fourth transistor of said first conductivity type having a base, an emitter and collector, said emitter being coupled to said first input of said second circuit means, said base being coupled to said emitter of said third transistor, and said collector being coupled to said output of said second circuit means.
Claim 10
Dependent Claim
100 words
The interface circuit of claim 8 wherein said comparator means of said second circuit means further includes a fifth transistor of said second conductivity type having an emitter, a base, a first collector, and a second collector, said emitter being coupled to said power supply, said base being coupled with said first collector to said collector of said fourth transistor, said second collector being coupled to said output of said second circuit means, said first and second collectors being area ratioed with respect to each other with said first collector having a greater area in relation to said second collector.
Claim 11
Dependent Claim
65 words
The interface circuit of claim 1 wherein said second circuit means includes: voltage translation means adapted to receive said second reference voltage level for translating the same upward to a third reference voltage level; and comparator means for comparing the magnitude of the input signal to said third reference voltage level for providing the second output signal at the output of said second circuit means.
Claim 12
Dependent Claim
60 words
The interface circuit of claim 10 wherein said voltage translation means includes a first transistor of first conductivity type having a base, emitter, and collector, said base being said second input of said second circuit means, said collector being coupled to a terminal at which is supplied a ground reference potential, and said emitter being coupled to a current source.
Claim 13
Dependent Claim
63 words
The interface circuit of claim 11 wherein said comparator means includes a second transistor of a second conductivity type having a base, an emitter and collector, said emitter being coupled to said first input of said second circuit means, said base being coupled to said emitter of said first transistor, and said collector being coupled to said output of said second circuit means.
Claim 14
Dependent Claim
95 words
The interface circuit of claim 12 wherein said comparator means further includes a third transistor of said first conductivity type having an emitter, a base, a first collector, and a second collector, said emitter being coupled to a power supply, said base being coupled with said first collector to said collector of said second transistor, said second collector being coupled to said output of said second circuit means, said first and second collectors being area ratioed with respect to each other with said first collector having a greater area in relation to said second collector.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-11-08 | 1986-05-10 | 1986-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-11-08 | 1990-05-10 | 1990-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-11-08 | 1994-05-10 | 1994-11-09 | $7700.00 | Window Closed / Lapsed |