US3873853A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Comparator-keyed oscillator
Assignee: RCA Corp
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Filing: 1973-08-09
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Granted: 1975-03-25
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Expires: 1993-08-09
Abstract
Abstract A dead-zone comparator includes first and second voltage comparators used respectively to compare an input signal to a high reference level and to a low reference level, which reference levels can be programmed. A bistable memory element is set by the output signal of one comparator and reset by the output signal of the other. These SET and RESET signals are opposite polarity currents, one of which is more severely constrained in value than the other, and are applied via a common SET-RESET buss to the memory element. When the memory element is in its SET condition, a relaxation oscillator is permitted to deliver output pulses of sufficient magnitude to trigger SCR''s or triacs directly. When the memory element is in its RESET condition, the relaxation oscillator is prevented from furnishing any output pulses.
Inventors
- 👤 Adel Abdel Aziz Ahmed
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:50
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/08; H02M1/081; G; G05; G05F; G05F1/00; G05F1/10; G05F1/12; G05F1/40; G05F1/44; G05F1/445; G05F1/45; G05F1/455
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
185 words
A voltage comparator comprising: first and second differential amplifiers each having first and second input circuits and an output circuit, said first input circuits of said first and said second differential amplifiers being connected together for receiving an input voltage to be compared to first and second referEnce voltages applied to their respective said second input circuits; a bistable memory element having a set circuit and a reset circuit respectively connected to separate ones of the output circuits of said first and said second differential amplifiers, having an output circuit, and being operable to provide at its said output circuit an output signal at one of first and second levels, alternatively available in response to the comparison of said input voltage to said first and said second reference voltages by said first and said second differential amplifiers; an oscillator having an output circuit from which oscillations are supplied; and an AND gate having a first input circuit connected to receive said memory output signal, having a second input circuit connected to said oscillator output circuit, and having an output circuit for supplying said recurrent pulses.
Claim 2
Dependent Claim
185 words
A voltage comparator comprising: first and second differential amplifiers each having first and second input circuits and an output circuit, said first input circuits of said first and said second differential amplifiers being connected together for receiving an input voltage to be compared to first and second referEnce voltages applied to their respective said second input circuits; a bistable memory element having a set circuit and a reset circuit respectively connected to separate ones of the output circuits of said first and said second differential amplifiers, having an output circuit, and being operable to provide at its said output circuit an output signal at one of first and second levels, alternatively available in response to the comparison of said input voltage to said first and said second reference voltages by said first and said second differential amplifiers; an oscillator having an output circuit from which oscillations are supplied; and an AND gate having a first input circuit connected to receive said memory output signal, having a second input circuit connected to said oscillator output circuit, and having an output circuit for supplying said recurrent pulses.
Claim 3
Dependent Claim
41 words
A voltage comparator as claimed in claim 1, further including: a triggered semiconductor switching device having a triggering circuit coupled to said AND gate output circuit to receive said recurrent pulses, said recurrent pulses serving as trigger pulses for said device.
Claim 4
Dependent Claim
201 words
A voltage comparator comprising: first and second differential amplifiers each having first and second input circuits and an output circuit, said first input circuits of said first and said second differential amplifiers being connected together for receiving an input voltage to be compared to first and second reference voltages applied to their respective said second input circuits; a bistable memory element having a set circuit and a reset circuit respectively connected to the respective output circuits of said first and said second differential amplifiers, having an output circuit and being operable to provide at its said output circuit an output signal at one of first and second levels, alternatively available in response to the comparison of said input voltage to said first and said second reference voltages by said first and said second differential amplifiers; means responsive to said memory output signal for supplying recurrent pulses only when said output signal is at said first level; and a triggered semiconductor switching device having a triggering circuit coupled to said means for supplying recurrent pulses to receive said recurrent pulses therefrom and having an output circuit which is enabled to conduct after triggering by the recurrent pulses received by its triggering circuit.
Claim 5
Dependent Claim
201 words
A voltage comparator comprising: first and second differential amplifiers each having first and second input circuits and an output circuit, said first input circuits of said first and said second differential amplifiers being connected together for receiving an input voltage to be compared to first and second reference voltages applied to their respective said second input circuits; a bistable memory element having a set circuit and a reset circuit respectively connected to the respective output circuits of said first and said second differential amplifiers, having an output circuit and being operable to provide at its said output circuit an output signal at one of first and second levels, alternatively available in response to the comparison of said input voltage to said first and said second reference voltages by said first and said second differential amplifiers; means responsive to said memory output signal for supplying recurrent pulses only when said output signal is at said first level; and a triggered semiconductor switching device having a triggering circuit coupled to said means for supplying recurrent pulses to receive said recurrent pulses therefrom and having an output circuit which is enabled to conduct after triggering by the recurrent pulses received by its triggering circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-24 | 1978-09-23 | 1979-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-24 | 1982-09-23 | 1983-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-24 | 1986-09-23 | 1987-03-25 | $7700.00 | Window Closed / Lapsed |