Level clamp for Tri-state CMOS bus structure

Claim 2

An active bus line clamp for clamping a multi-state bus line of a CMOS system to a particular logic level, the bus line being set to different logic levels by at least one driving means connected thereto, the level of the bus line tending to drift if not clamped and if the bus line is not being driven by the at least one driving means, the clamp comprising: a non-inverting CMOS buffer driver connected to the bus line for tapping power therefrom, the power being represented as voltages at an input and an output of the buffer driver; wherein the CMOS buffer driver comprises a first set of low impedance P and N transistors connected to a second set of low power P and N transistors; and a resistor having a first end connected to the input and a second end connected to the output of the buffer driver for limiting differences in the voltages between the input and the output of the buffer driver by draining current to or supplying current from the bus line, thereby automatically clamping the bus line at the logic level at which the bus line was last set by the driving means.

Claim 3

In a CMOS system having a three-state bus structure containing a plurality of bus lines having a tendency to drift from a first state to a second state, a plurality of drivers and gates connected to at least one of the bus lines, each of the drivers being adaptable to drive the bus line to different logic states each having a predetermined logic level voltage, an apparatus for clamping the bus line to a particular logic state, the apparatus comprising: a non-inverting gate having an input tapped onto the bus line for sensing the logic level voltage existing therealong; and a resistor means, the two ends of which are connected to the input and an output, respectively, of the non-inverting gate, for regulating therethrough the flow of current to or from the bus line so as to maintain substantially identical voltages at the input and the output of the non-inverting gate; wherein, if the logic level voltage on the bus line were to drift, the apparatus automatically clamps the voltage on the bus line to whatever logic level voltage it was last set by draining or sourcing current caused by the logic level voltage drift through the resistor means.

Claim 4

In a CMOS system having a three-state bus structure containing a plurality of bus lines having a tendency to drift from a first state to a second state, a plurality of drivers and gates connected to at least one of the bus lines, each of the drivers being adaptable to drive the bus line to different logic states each having a predetermined logic level voltage, an apparatus for clamping the bus line to a particular logic state, the apparatus comprising: a non-inverting gate having an input tapped onto the bus line for sensing the logic level voltage existing therealong; and a resistor means, the two ends of which are connected to the input and an output, respectively, of the non-inverting gate, for regulating therethrough the flow of current to or from the bus line so as to maintain substantially identical voltages at the input and the output of the non-inverting gate; wherein, if the logic level voltage on the bus line were to drift, the apparatus automatically clamps the voltage on the bus line to whatever logic level voltage it was last set by draining or sourcing current caused by the logic level voltage drift through the resistor means.

Claim 5

Apparatus as set forth in claim 2, wherein the noninverting gate comprises a CMOS buffer driver.

Claim 6

An active bus line clamp for clamping a multi-state bus line of a CMOS system to a particular logic level, comprising: a non-inverting buffer driver connected to the bus line for tapping power therefrom, the power being represented as voltages at an input and an output of the buffer driver; and a resistor having a first end connected to the input and a second end connected to the output of the buffer driver for automatically limiting differences in the voltages between the input and the output of the buffer driver by draining current to or supplying current from the bus line, thereby automatically clamping the bus line at whatever logic level it was last driven by any one of a plurality of drivers connected to the bus line, the drivers adapted to drive the bus line to different logic levels.

Claim 7

An active bus line clamp for clamping a multi-state bus line of a CMOS system to a particular logic level, comprising: a non-inverting buffer driver connected to the bus line for tapping power therefrom, the power being represented as voltages at an input and an output of the buffer driver; and a resistor having a first end connected to the input and a second end connected to the output of the buffer driver for automatically limiting differences in the voltages between the input and the output of the buffer driver by draining current to or supplying current from the bus line, thereby automatically clamping the bus line at whatever logic level it was last driven by any one of a plurality of drivers connected to the bus line, the drivers adapted to drive the bus line to different logic levels.