Patent US5329157A successfully refreshed from Google Patents.
US5329157A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area
Assignee: LSI Corp
•
Filing: 1992-08-21
•
Granted: 1994-07-12
•
Expires: 2012-08-21
Abstract
Abstract A greater lead count for a given die area can be achieved with "certain non-square" geometries formed by the inner ends of conductive lines. These include various triangular configurations, as well as "greatly elongated" rectangular, parallelogram and trapezoidal configurations. The conductive lines may be leads of a lead frame, leads on a tape-based package, or traces on ceramic or PCB-substrate packages. The package body may be formed to have a shape similar to that of the die receiving area, and may also be provided with external pins, ball bumps or leads. A number of these "certain non-square" packages may be assembled in an electronic system on a mother board. Unpackaged "certain non-square" dies may be connected to the ends of traces on a substrate, and encapsulated to form a multi-chip module.
Inventors
- 👤 Michael D. Rosotker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:59
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/90; G; G03; G03F; G03F7/00; G03F7/70; G03F7/70425; G03F7/70433; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/392; H10D; H10D62/00; H10D62/10; H10D62/117; H10D89/00; H10D89/10; H10W70/00; H10W70/40; H10W70/411; H10W70/421; H10W70/435; H10W74/00; H10W74/10; H10W74/111; H10W74/124; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/20; H10W72/29; H10W72/50; H10W72/531; H10W72/5363; H10W72/541; H10W72/5449; H10W72/547; H10W72/551; H10W72/552; H10W72/5522; H10W72/59; H10W72/931; H10W72/932; H10W72/951; H10W90/00; H10W90/701; H10W90/721; H10W90/722; Y; Y10; Y10S; Y10S148/00; Y10S148/028
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
94 words
A patterned layer of conductive lines defining a die-receiving area for packaging a semiconductor die, comprising: a plurality of conductive lines, said conductive lines having inner ends; the inner ends of said conductive lines defining a certain non-square die-receiving area for mounting a semiconductive die; wherein: the geometric configuration formed by the inner ends of the conductive lines define a triangular shaped die-receiving area, said die-receiving area having angles alpha, beta, and phi; the die-receiving area is a right isosceles triangle; and the angles alpha, beta and phi are 45°, 45°, and 90°, respectively.
Claim 2
Dependent Claim
94 words
A patterned layer of conductive lines defining a die-receiving area for packaging a semiconductor die, comprising: a plurality of conductive lines, said conductive lines having inner ends; the inner ends of said conductive lines defining a certain non-square die-receiving area for mounting a semiconductive die; wherein: the geometric configuration formed by the inner ends of the conductive lines define a triangular shaped die-receiving area, said die-receiving area having angles alpha, beta, and phi; the die-receiving area is a right isosceles triangle; and the angles alpha, beta and phi are 45°, 45°, and 90°, respectively.
Claim 3
Dependent Claim
39 words
A patterned layer of conductive lines, according to claim 1, further comprising: certain non-square a die attach pad for supporting the semiconductor die; wherein the die attach pad has a shape similar to the shape of the die-receiving area.
Claim 4
Dependent Claim
18 words
A patterned layer of conductive lines, according to claim 1, wherein: the conductive lines are lead frame leads.
Claim 5
Dependent Claim
20 words
A patterned layer of conductive lines, according to claim 1, wherein: the conductive lines are leads in a tape-based package.
Claim 6
Dependent Claim
20 words
A patterned layer of conductive lines, according to claim 1, wherein: the conductive lines are traces on a ceramic layer.
Claim 7
Dependent Claim
19 words
A patterned layer of conductive lines, according to claim 1, wherein: the conductive lines are traces on a PCB-substrate.
Claim 8
Dependent Claim
91 words
A patterned layer of conductive lines defining a die-receiving area for packaging a semiconductor die, comprising: a plurality of conductive lines, said conductive lines having inner ends; the inner ends of said conductive lines defining a certain non-square die-receiving area for mounting a semiconductor die; wherein: the geometric configuration formed by the inner ends of the conductive lines define a triangular shaped die-receiving area, said die-receiving area having angles alpha, beta, and phi; the die-receiving area is triangular; and the angles alpha, beta and phi are 30°, 60°, and 90°, respectively.
Claim 9
Dependent Claim
91 words
A patterned layer of conductive lines defining a die-receiving area for packaging a semiconductor die, comprising: a plurality of conductive lines, said conductive lines having inner ends; the inner ends of said conductive lines defining a certain non-square die-receiving area for mounting a semiconductor die; wherein: the geometric configuration formed by the inner ends of the conductive lines define a triangular shaped die-receiving area, said die-receiving area having angles alpha, beta, and phi; the die-receiving area is triangular; and the angles alpha, beta and phi are 30°, 60°, and 90°, respectively.
Claim 10
Dependent Claim
39 words
A patterned layer of conductive lines, according to claim 7, further comprising: a certain non-square die attach pad for supporting the semiconductor die; wherein: the die attach pad has a shape similar to the shape of the die-receiving area.
Claim 11
Dependent Claim
18 words
A patterned layer of conductive lines, according to claim 7, wherein: the conductive lines are lead frame leads.
Claim 12
Dependent Claim
20 words
A patterned layer of conductive lines, according to claim 7, wherein: the conductive lines are leads in a tape-based package.
Claim 13
Dependent Claim
20 words
A patterned layer of conductive lines, according to claim 7, wherein: the conductive lines are traces on a ceramic layer.
Claim 14
Dependent Claim
19 words
A patterned layer of conductive lines, according to claim 7, wherein: the conductive lines are traces on a PCB-substrate.
Claim 15
Dependent Claim
64 words
A patterned layer of conductive lines defining a die-receiving area for packaging a semiconductor die, comprising: a plurality of conductive lines, said conductive lines having inner ends; the inner ends of said conductive lines defining a certain non-square die-receiving area for mounting a semiconductor die; wherein: the geometric configuration formed by the inner ends of the conductive lines define a trapezoidal shaped die-receiving area.
Claim 16
Dependent Claim
64 words
A patterned layer of conductive lines defining a die-receiving area for packaging a semiconductor die, comprising: a plurality of conductive lines, said conductive lines having inner ends; the inner ends of said conductive lines defining a certain non-square die-receiving area for mounting a semiconductor die; wherein: the geometric configuration formed by the inner ends of the conductive lines define a trapezoidal shaped die-receiving area.
Claim 17
Dependent Claim
37 words
A patterned layer of conductive lines, according to claim 9, further comprising: a die attach pad for supporting the semiconductor die; wherein: the die attach pad has a shape similar to the shape of the die-receiving area.
Claim 18
Dependent Claim
18 words
A patterned layer of conductive lines, according to claim 13, wherein: the conductive lines are lead frame leads.
Claim 19
Dependent Claim
20 words
A patterned layer of conductive lines, according to claim 13, wherein: the conductive lines are leads in a tape-based package.
Claim 20
Dependent Claim
20 words
A patterned layer of conductive lines, according to claim 13, wherein: the conductive lines are traces on a ceramic layer.
Claim 21
Dependent Claim
19 words
A patterned layer of conductive lines, according to claim 13, wherein: the conductive lines are traces on a PCB-substrate.
References Cited (Backward Citations)
US3169837A
Cited
US4253280A
Cited
JPS567471A
Cited
JPS5658234A
Cited
JPS56122175A
Cited
US4413404A
Cited
DE3048362A1
Cited
JPS57143844A
Cited
JPS58207646A
Cited
US4542397A
Cited
US4903114A
Cited
EP0247644A1
Cited
EP0259222A2
Cited
GB2196475A
Cited
US4771330A
Cited
US4918614A
Cited
EP0311513A2
Cited
JPH01270245A
Cited
US5233220A
Cited
US5182233A
Cited
US5173369A
Cited
JPH03280448A
Cited
JPH04162640A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-11 | 1998-01-10 | 1998-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-11 | 2002-01-10 | 2002-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-11 | 2006-01-10 | 2006-07-12 | $7700.00 | Window Closed / Lapsed |