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JPS5658234A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor integrated circuit

Assignee: Seiko Epson Corp
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Filing: 1979-10-17
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Granted: —
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Expires: 1999-10-17
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Abstract

Abstract PURPOSE:To increase efficiency of utilization of a wafer by a method wherein an IC chip having a larger area is provided in the center of an Si single crystal wafer and at the same time a small-chip-sized IC is formed on the peripheral section of the IC chip. CONSTITUTION:Using a mask whereon an IC pattern 9 with a large chip size is arranged in the cente of a glass substrate 8 and an IC pattern 10 with a small chip size is arranged on the surrounding region, IC patterns 6 and 7 having a different chip size are formed on an Si substrate 5 simultaneously. With this constitution, a wafer is utilized effectively and the cost of the chips can be cut down.

Inventors

  • 👤 Koichi Oguchi

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 19:37
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70425; G03F7/70433; H; H10; H10P; H10P95/00

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