Patent US5324981A successfully refreshed from Google Patents.
US5324981A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Field effect transistor device with contact in groove
Assignee: Mitsubishi Electric Corp
•
Filing: 1993-04-14
•
Granted: 1994-06-28
•
Expires: 2013-04-14
Abstract
Abstract A high power FET device includes a plated heat sink, a rear surface electrode disposed between a substrate and the heat sink, a via-hole extending through the substrate and containing a metal plating for electrically connecting the rear surface electrode and an element, such as the source electrode, of the FET device. A metallic layer extending from the rear surface to the front surface of the device protects the side walls of the substrate during handling. The side wall protection layer extends onto portions of the front surface of the substrate as a measurement electrode. The arrangement gives access to the source, drain, and gate electrodes of the device from the front surface for measuring the electrical characteristics of the device while it is still part of a wafer containing a large number of devices. Each device includes a separation groove outwardly spaced from the device and containing a metallic layer which becomes the side wall protection layer after dicing. Preferably, the separation grooves are wider and deeper than the via-holes.
Inventors
- 👤 Michihiro Kobiki
- 👤 Masahiro Yoshida
- 👤 Takahide Ishikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 12:51
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/273; H10P54/00; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0245; H10W20/20; H10W40/00; H10W40/10; H10W42/00; H10W42/121; Y; Y10; Y10S; Y10S148/00; Y10S148/028; Y10S438/00; Y10S438/977
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
148 words
A semiconductor device assembly comprising: a semiconductor wafer having opposed front and rear surfaces, said wafer being a common substrate; a plurality of substantially identical semiconductor devices formed on said wafer, each device including at least one via-hole extending into said wafer from said front surface toward said rear surface; at least one circumferential separation groove extending into said wafer from said front surface toward said rear surface farther than said at least one via-hole and lying outwardly from a first of said semiconductor devices for separation of said first semiconductor device from said wafer; a first metallic electrode disposed in said at least one via-hole for electrically connecting said respective semiconductor devices at said front surface; and a metal layer disposed in said at least one separation groove for forming a metal protection layer on surfaces of said semiconductor devices when they are separated from said wafer.
Claim 2
Dependent Claim
148 words
A semiconductor device assembly comprising: a semiconductor wafer having opposed front and rear surfaces, said wafer being a common substrate; a plurality of substantially identical semiconductor devices formed on said wafer, each device including at least one via-hole extending into said wafer from said front surface toward said rear surface; at least one circumferential separation groove extending into said wafer from said front surface toward said rear surface farther than said at least one via-hole and lying outwardly from a first of said semiconductor devices for separation of said first semiconductor device from said wafer; a first metallic electrode disposed in said at least one via-hole for electrically connecting said respective semiconductor devices at said front surface; and a metal layer disposed in said at least one separation groove for forming a metal protection layer on surfaces of said semiconductor devices when they are separated from said wafer.
Claim 3
Dependent Claim
22 words
The semiconductor device assembly of claim 1 wherein said at least one separation groove is wider than said at least one via-hole.
Claim 4
Dependent Claim
18 words
The semiconductor device assembly of claim 1 wherein said first metallic electrode and said metal layer are gold.
Claim 5
Dependent Claim
50 words
The semiconductor device assembly of claim 1 wherein said metal layer extends over portions of the front surface of said first semiconductor device from said at least one separation groove to form a measurement electrode for measuring electrical characteristics of said first semiconductor device before its separation from said wafer.
Claim 6
Dependent Claim
39 words
The semiconductor device assembly of claim 4 including a second metallic electrode disposed on the rear surface of said substrate in electrical communication with said first metallic electrode at said at least one via-hole and with said metal layer.
Claim 7
Dependent Claim
18 words
The semiconductor device assembly of claim 5 including a plated heat sink disposed on said second metallic electrode.
Claim 8
Dependent Claim
47 words
The semiconductor device assembly of claim 1 wherein said semiconductor devices are field effect transistors, each including an active region in said wafer at said front surface and a source electrode, a drain electrode, and a gate electrode disposed on said front surface at said active region.
Claim 9
Dependent Claim
32 words
The semiconductor device assembly of claim 7 wherein said gate electrode forms a Schottky barrier with said active region and said source and drain electrodes form ohmic contacts with said active region.
Claim 10
Dependent Claim
12 words
The semiconductor device assembly of claim 1 wherein said wafer is GaAs.
References Cited (Backward Citations)
GB633848A
Cited
GB864121A
Cited
FR1425906A
Cited
GB1099381A
Cited
US4180422A
Cited
US3938176A
Cited
GB1476585A
Cited
US3986196A
Cited
FR2318350A1
Cited
US4219827A
Cited
US4023260A
Cited
US4237600A
Cited
US4384400A
Cited
US4486767A
Cited
EP0041890A1
Cited
JPS5994818A
Cited
US4532699A
Cited
JPS59117171A
Cited
GB2136203A
Cited
EP0142216A1
Cited
GB2150749A
Cited
US4537654A
Cited
JPS6177369A
Cited
EP0188879A2
Cited
GB2182200A
Cited
JPS6294965A
Cited
JPS62122279A
Cited
JPS62122278A
Cited
JPS62211962A
Cited
JPS63155673A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |