Method of fabricating a thin-film transistor and wiring matrix device

Claim 1

A method of fabricating a thin-film transistor device including a multi-layer wiring section, comprising the steps of: a first depositing step of depositing in a transistor region of a substrate a first conducting layer; a second depositing step of depositing in a wiring region of said substrate a first conducting wiring layer; a third depositing step of simultaneously depositing both a gate insulating layer made of inorganic material over said first conducting layer and a wiring insulating layer made of inorganic material over said first conducting wiring layer; forming a thin-film transistor, including said first conducting layer and said gate insulating layer, over said wiring insulating layer, said forming step includes depositing a layer of amorphous semiconducting silicon over said wiring insulating layer; a fourth depositing step of depositing an organic insulating layer on said wiring insulating layer, wherein said third and fourth depositing steps deposit said wiring insulating layer and said organic insulating layer to a total thickness of less than 1.3 microns; a fifth depositing step of depositing a second conducting wiring layer over said wiring insulating layer and contacting said first conducting wiring layer, such that said transistor includes a drain electrode and a source electrode, wherein said first and second depositing steps are performed simultaneously, said multi-layer wiring section including an electrode formed by said first conducting wiring layer, wherein a line from said drain electrode of the transistor is coupled to said electrode of the multi-layer wiring section through a through-hole formed in said multi-layer wiring section.

Claim 2

A method of fabricating a thin-film transistor device including a multi-layer wiring section, comprising the steps of: a first depositing step of depositing in a transistor region of a substrate a first conducting layer; a second depositing step of depositing in a wiring region of said substrate a first conducting wiring layer; a third depositing step of simultaneously depositing both a gate insulating layer made of inorganic material over said first conducting layer and a wiring insulating layer made of inorganic material over said first conducting wiring layer; forming a thin-film transistor, including said first conducting layer and said gate insulating layer, over said wiring insulating layer, said forming step includes depositing a layer of amorphous semiconducting silicon over said wiring insulating layer; a fourth depositing step of depositing an organic insulating layer on said wiring insulating layer, wherein said third and fourth depositing steps deposit said wiring insulating layer and said organic insulating layer to a total thickness of less than 1.3 microns; a fifth depositing step of depositing a second conducting wiring layer over said wiring insulating layer and contacting said first conducting wiring layer, such that said transistor includes a drain electrode and a source electrode, wherein said first and second depositing steps are performed simultaneously, said multi-layer wiring section including an electrode formed by said first conducting wiring layer, wherein a line from said drain electrode of the transistor is coupled to said electrode of the multi-layer wiring section through a through-hole formed in said multi-layer wiring section.

Claim 7

A method for fabricating an array of thin-film transistor devices, said method comprising the steps of: fabricating a plurality of said thin-film transistor devices disposed in a line by performing the steps of: a first depositing step of depositing in a transistor region of a substrate a first conducting layer; a second depositing step of depositing in a wiring region of said substrate a first conducting wiring layer; a third depositing step of simultaneously depositing both a gate insulating layer made of inorganic material over said first conducting layer and a wiring insulating layer made of inorganic material over said first conducting wiring layer; forming a thin-film transistor, including said first conducting layer and said gate insulating layer, over said wiring insulating layer, said forming step includes depositing a layer of amorphous semiconducting silicon over said wiring insulating layer; a fourth depositing step of depositing an organic insulating layer on said wiring insulating layer, wherein said third and fourth depositing steps deposit said wiring insulating layer and said organic insulating layer to a total thickness of less than 1.3 microns; a fifth depositing step of depositing a second conducting wiring layer over said wiring insulating layer and contacting said first conducting wiring layer, such that said transistor includes a drain electrode and a source electrode, wherein said first and second depositing steps are performed simultaneously, said multi-layer wiring section including an electrode formed by said first conducting wiring layer, wherein a line from said drain electrode of the transistor is coupled to said electrode of the multi-layer wiring section through a through-hole formed in said multi-layer wiring section.

Claim 8

A method for fabricating an array of thin-film transistor devices, said method comprising the steps of: fabricating a plurality of said thin-film transistor devices disposed in a line by performing the steps of: a first depositing step of depositing in a transistor region of a substrate a first conducting layer; a second depositing step of depositing in a wiring region of said substrate a first conducting wiring layer; a third depositing step of simultaneously depositing both a gate insulating layer made of inorganic material over said first conducting layer and a wiring insulating layer made of inorganic material over said first conducting wiring layer; forming a thin-film transistor, including said first conducting layer and said gate insulating layer, over said wiring insulating layer, said forming step includes depositing a layer of amorphous semiconducting silicon over said wiring insulating layer; a fourth depositing step of depositing an organic insulating layer on said wiring insulating layer, wherein said third and fourth depositing steps deposit said wiring insulating layer and said organic insulating layer to a total thickness of less than 1.3 microns; a fifth depositing step of depositing a second conducting wiring layer over said wiring insulating layer and contacting said first conducting wiring layer, such that said transistor includes a drain electrode and a source electrode, wherein said first and second depositing steps are performed simultaneously, said multi-layer wiring section including an electrode formed by said first conducting wiring layer, wherein a line from said drain electrode of the transistor is coupled to said electrode of the multi-layer wiring section through a through-hole formed in said multi-layer wiring section.