US5287511A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith
Assignee: Logic Devices Inc
•
Filing: 1991-10-15
•
Granted: 1994-02-15
•
Expires: 2011-10-15
Abstract
Abstract Architectures and methods are provided for efficiently dividing a processing task into tasks for a programmable real time signal processor (SPROC) and tasks for a decision-making microprocessor. The SPROC is provided with a non-interrupt structure where data flow is through a multiported central memory. The SPROC is also programmed in an environment which requires nothing more than graphic entry of a block diagram of the user's design. In automatically implementing the block diagram into silicon, the SPROC programming/development environment accounts for and provides software connection and interfaces with a host microprocessor. The programming environment preferably includes: a high-level computer screen entry system which permits choosing, entry, parameterization, and connection of a plurality of functional blocks; a functional block cell library which provides source code representing the functional blocks; and a signal processor scheduler/compiler which uses the functional block cell library and the information entered into the high-level entry system to compile a program and to output source program code for a program memory and source data code for the data memory of the (SPROC), as well as a symbol table which provides a memory map which maps SPROC addresses to variable names which the microprocessor will refer to in separately compiling its program.
Inventors
- 👤 Jeffrey I. Robinson
- 👤 Keith Rouse
- 👤 Andrew J. Krassowski
- 👤 Terry F. Montlick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:04
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/355; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F11/3698; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/177; G06F15/76; G06F15/78; G06F15/7828; G06F15/7835; G06F15/7839; G06F15/7842; G06F15/786; G06F15/80; G06F15/8007; G06F15/8015; G06F30/00; G06F30/30; G06F8/00; G06F8/30; G06F8/34; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/32; G06F9/322; G06F9/325; G06F9/38; G06F9/3877; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/025
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
480 words
Apparatus for providing program code for a real time signal processor means having a memory means, and for concurrently generating memory access code for use by a host processor means so that the host processor means can change the contents of the memory of the signal processor means, wherein object code for the signal processor means and the host processor means are separately compiled by a respective signal processor compiler and a host processor compiler, and the signal processor means and the host processor means each include means for interfacing with each other, said apparatus comprising: means for describing a block diagram representing a processing task for the signal processor means with a plurality of high level signal processing functional block means and a plurality of connections between said high level signal processing functional block means, each functional block means having a name, at least one of said functional block means having a parameter, and at least one of said functional block means having an indication of being accessible by the host processor means; signal processor cell library means containing a plurality of source code blocks, each source code block representing at least a portion of a corresponding high level signal processing functional block means, at least one of said source code blocks containing a named variable for receiving a value for said parameter; and signal processor compiler means coupled to said means for describing and to said signal processor cell library means, for analyzing said block diagrm, for obtaining code blocks from said signal processor cell library means needed to implement said block diagram, for associating said named variable with said parameter, and for compiling said code blocks to provide program code and data code for the memory means of the signal processing means, and a correspondence table associating at least one signal processor means memory location with said named cell variable, said correspondence table being for the host processor means such that said correspondence table of a translation thereof is used by the host processor compiler in the compiling of the object code for the host processor means, and the object code for the host processor means causes the host processor means to access the memory location of the signal processor means via the interface means of the host processor means and the signal processor means so that the host processor means can change said parameter value, wherein said program code and data code will cause the signal processor means to implement said processing task for the signal processor means, with said program code controlling the functioning of the real time signal processor means, and said data code providing initial parameter values for the signal processor means and initial sample data values for memory locations in the memory means of the signal processor means, and wherein said parameter values represent values of parameters of said functional block means.
Claim 2
Dependent Claim
480 words
Apparatus for providing program code for a real time signal processor means having a memory means, and for concurrently generating memory access code for use by a host processor means so that the host processor means can change the contents of the memory of the signal processor means, wherein object code for the signal processor means and the host processor means are separately compiled by a respective signal processor compiler and a host processor compiler, and the signal processor means and the host processor means each include means for interfacing with each other, said apparatus comprising: means for describing a block diagram representing a processing task for the signal processor means with a plurality of high level signal processing functional block means and a plurality of connections between said high level signal processing functional block means, each functional block means having a name, at least one of said functional block means having a parameter, and at least one of said functional block means having an indication of being accessible by the host processor means; signal processor cell library means containing a plurality of source code blocks, each source code block representing at least a portion of a corresponding high level signal processing functional block means, at least one of said source code blocks containing a named variable for receiving a value for said parameter; and signal processor compiler means coupled to said means for describing and to said signal processor cell library means, for analyzing said block diagrm, for obtaining code blocks from said signal processor cell library means needed to implement said block diagram, for associating said named variable with said parameter, and for compiling said code blocks to provide program code and data code for the memory means of the signal processing means, and a correspondence table associating at least one signal processor means memory location with said named cell variable, said correspondence table being for the host processor means such that said correspondence table of a translation thereof is used by the host processor compiler in the compiling of the object code for the host processor means, and the object code for the host processor means causes the host processor means to access the memory location of the signal processor means via the interface means of the host processor means and the signal processor means so that the host processor means can change said parameter value, wherein said program code and data code will cause the signal processor means to implement said processing task for the signal processor means, with said program code controlling the functioning of the real time signal processor means, and said data code providing initial parameter values for the signal processor means and initial sample data values for memory locations in the memory means of the signal processor means, and wherein said parameter values represent values of parameters of said functional block means.
Claim 3
Dependent Claim
35 words
Apparatus according to claim 1, wherein: said means for describing a block diagram comprises a high-level computer screen entry system means for choosing, entry, parameterization, and connection of a plurality of said functional block means.
Claim 4
Dependent Claim
19 words
Apparatus according to claim 2, wherein: said means for describing a block diagram further comprises a text editor means.
Claim 5
Dependent Claim
99 words
Apparatus according to claim 1, wherein: said means for describing a block diagram comprises means for representing a processing task for the host processor means with a plurality of high level host processor functional block means and a plurality of connections between said plurality of high level host processor functional block means, each host processor functional block means having a name, wherein said means for describing further comprises means for distinguishing between portions of said block diagram intended for compilation by the signal processor means and portions of said block diagram intended for compilation by the host processor means.
Claim 6
Dependent Claim
51 words
Apparatus according to claim 1, further comprising: means for generating from said program code and said data code signal processor means boot code suitable for compilation by the compiler of the host processor means, wherein the host processor means can use said boot code to boot up the signal processor means.
Claim 7
Dependent Claim
36 words
Apparatus according to claim 1, further comprising: correspondence table translation means for translating said correspondence table generated by the signal processor compiler means into code suitable for compilation by the compiler for the host processor means.
Claim 8
Dependent Claim
36 words
Apparatus according to claim 5, further comprising: correspondence table translation means for translating said correspondence table generated by said signal processor compiler means into code suitable for compilation by the compiler for the host processor means.
Claim 9
Dependent Claim
11 words
Apparatus according to claim 1, further comprising: the signal processor means.
Claim 10
Dependent Claim
346 words
Apparatus according to claim 8, wherein: said signal processor means receives real time data signals from means other than the host processor and external said apparatus, and said signal processor means processes said real time data signals thereby generating processed real time data signals which are available external to said signal processor means, and said signal processor means comprises at least one real time data signal receiving means for receiving said real time data signals, each real time data signal receiving means including means for writing data to desired first address locations in a multiported central memory unit in a repeated sequential fashion; said multiported central memory unit coupled to said at least one real time data signal receiving means, said multiported central memory unit for storing said received data signals and said data code and comprising the memory means; a digital processor means coupled to said multiported central memory unit, for obtaining said real time data signals from said first addresses of said multiported central memory unit, for processing said real time data signals and thereby generating processed data signals, and for sending said processed data signals for storage in second address locations of said multiported central memory unit; at least one data output means coupled to said multiported central memory unit, for obtaining in a repeated sequential fashion said processed data signals from said second address locations of said multiported central memory unit, and for making said processed data signals available external to said signal processor means as real time processed data signals, said memory means further including program memory means coupled to said digital processor means for storing said program code, wherein said digital processor means processes said real time data signals according to said program code, wherein substantially all signal data received by said signal processor means flows through said multiported central memory unit, and wherein said real time data signal receiving means and said output means handle data flow into and out of said signal processor means and permit said digital processor means to function substantially free of data input interrupts.
Claim 11
Dependent Claim
41 words
Apparatus according to claim 9, wherein: said signal processor means further comprises a parallel host port coupled to said program memory means and to said multiported central memory means, wherein said host port comprises the interface to the host processor means.
Claim 12
Dependent Claim
11 words
Apparatus according to claim 8, further comprising: the host processor means.
Claim 13
Dependent Claim
11 words
Apparatus according to claim 1, further comprising: the host processor means.
Claim 14
Dependent Claim
13 words
Apparatus according to claim 12 wherein: said host processor means comprises a microprocessor.
Claim 15
Dependent Claim
328 words
Method for providing program code for a real time signal processor means having a memory means, and for concurrently generating memory access code for use by a host processor means so that said host processor means can change the contents of the memory of said signal processor means, wherein object code for said signal processor means and said host processor means are separately compiled, and said signal processor means and said host processor means each include means for interfacing with each other, said method comprising: describing and representing a processing task for said signal processor means in a block diagram with a plurality of high level signal processing functional block means and a plurality of connections between said high level signal processing functional block means, each functional block means having a name, at least one of said functional block means having a parameter, and at least one of said functional block means having an indication of being accessible by the host processor means; providing a signal processor cell library means containing a plurality of source code blocks, each source code block representing at least a portion of a corresponding high level signal processing functional block means, at least one of said source code blocks containing a named variable for receiving a value for said parameter; and analyzing said block digram in order to obtain needed code blocks from said signal processor cell library means for implementing said block diagram; associating said named variable with said parameter, and compiling said code blocks to provide program code and data code for the memory means of the signal processing means, and a correspondence table associating at least one signal processor memory location with said named cell variable, providing said correspondence table or a translation thereof for compilation as object code for said host processor means, wherein said correspondence table permits said host processor means to change a parameter value stored as a variable in said memory of said signal processor means.
Claim 16
Dependent Claim
328 words
Method for providing program code for a real time signal processor means having a memory means, and for concurrently generating memory access code for use by a host processor means so that said host processor means can change the contents of the memory of said signal processor means, wherein object code for said signal processor means and said host processor means are separately compiled, and said signal processor means and said host processor means each include means for interfacing with each other, said method comprising: describing and representing a processing task for said signal processor means in a block diagram with a plurality of high level signal processing functional block means and a plurality of connections between said high level signal processing functional block means, each functional block means having a name, at least one of said functional block means having a parameter, and at least one of said functional block means having an indication of being accessible by the host processor means; providing a signal processor cell library means containing a plurality of source code blocks, each source code block representing at least a portion of a corresponding high level signal processing functional block means, at least one of said source code blocks containing a named variable for receiving a value for said parameter; and analyzing said block digram in order to obtain needed code blocks from said signal processor cell library means for implementing said block diagram; associating said named variable with said parameter, and compiling said code blocks to provide program code and data code for the memory means of the signal processing means, and a correspondence table associating at least one signal processor memory location with said named cell variable, providing said correspondence table or a translation thereof for compilation as object code for said host processor means, wherein said correspondence table permits said host processor means to change a parameter value stored as a variable in said memory of said signal processor means.
Claim 17
Dependent Claim
69 words
A method according to claim 14, further comprising: providing said program code and data code to said signal processor, thereby implementing said tasks for said signal processor means, with said program code controlling how said signal processor means functions, and said data code providing initial parameter values for the signal processor means and initial sample data values for memory locations in the memory means of said signal processor means.
Claim 18
Dependent Claim
40 words
A method according to claim 14, further comprising: generating from said program code and said data code signal processor means boot code suitable for compilation by said compiler of said host processor or for direct storage in said host processor.
Claim 19
Dependent Claim
21 words
A method according to claim 14, further comprising: compiling said correspondence table or a translation thereof in said host processor compiler;
Claim 20
Dependent Claim
49 words
A method according to claim 16, further comprising: compiling said correspondence table or a translation thereof in said host processor compiler; storing said boot code in said host processor; and booting up said signal processor by providing said boot code stored in said host processor to said signal processor.
Claim 21
Independent Claim
206 words
An apparatus for coupling a host processor and a programmable signal processor having a memory for storing a program and data so that the host processor has intelligent access to the signal processor memory, said apparatus comprising: a) high level programming means for defining signal processor functions, said programming means including means for symbolically indicating host processor access to signal processor functions; b) signal processor program compiling means coupled to said programming means for generating signal processor program code which causes said signal processor to implement said signal processor functions and for generating memory access code for the host processor, said memory access code including a correspondence table correlating symbolic indications indicated in said programming means with memory addresses in the signal processor memory; c) host processor compiling means for generating host processor program code including reference to at least one of said memory addresses in said correspondence table, said host processor compiling means including means for receiving at least a portion of said memory access code; and d) interface means coupling the host processor and the signal processor memory, wherein said host processor program code causes the host processor to access the signal processor memory according to said symbolic indications indicated in said programming means.
Claim 22
Independent Claim
206 words
An apparatus for coupling a host processor and a programmable signal processor having a memory for storing a program and data so that the host processor has intelligent access to the signal processor memory, said apparatus comprising: a) high level programming means for defining signal processor functions, said programming means including means for symbolically indicating host processor access to signal processor functions; b) signal processor program compiling means coupled to said programming means for generating signal processor program code which causes said signal processor to implement said signal processor functions and for generating memory access code for the host processor, said memory access code including a correspondence table correlating symbolic indications indicated in said programming means with memory addresses in the signal processor memory; c) host processor compiling means for generating host processor program code including reference to at least one of said memory addresses in said correspondence table, said host processor compiling means including means for receiving at least a portion of said memory access code; and d) interface means coupling the host processor and the signal processor memory, wherein said host processor program code causes the host processor to access the signal processor memory according to said symbolic indications indicated in said programming means.
Claim 23
Dependent Claim
49 words
Apparatus according to claim 19, wherein: said host processor access to the signal processor memory is selected from the group consisting of reading a parameter value, writing a parameter value, reading a data value, writing a data value, reading signal processor program code and writing signal processor program code.
Claim 24
Dependent Claim
47 words
Apparatus according to claim 19, wherein: said symbolic indications of host processor access are selected from the group consisting of reading a parameter value, writing a parameter value, reading a data value, writing a data value, reading signal processor program code, and writing signal processor program code.
Claim 25
Dependent Claim
11 words
An apparatus according to claim 19, further comprising: the host processor.
Claim 26
Dependent Claim
12 words
An apparatus according to claim 19, further comprising: the programmable signal processor.
Claim 27
Dependent Claim
16 words
An apparatus according to claim 19, further comprising: the host processor; and the programmable signal processor.
Claim 28
Dependent Claim
171 words
Apparatus for defining access of a host processor which is interfaced with a programmable signal processor to permit the host processor to partially control the programmable signal processor, where the object codes of the host processor and the signal processor are separately compiled, and the programmable signal processor has a memory for storing the signal processor object code and data, said apparatus comprising: a) high level programming means for defining processing tasks for the signal processor, said programming means including means for indicating host processor access to at least a portion of one of said processing tasks; and b) signal processor program compiling means coupled to said high level programing means for generating the signal processor object code which implements said processing tasks, and for generating a memory address list for the host processor, said memory address list indicating memory addresses corresponding to the host processor access to said tasks indicated by said high level programming means, said memory address list being read or received by a host processor compiling means.
Claim 29
Dependent Claim
171 words
Apparatus for defining access of a host processor which is interfaced with a programmable signal processor to permit the host processor to partially control the programmable signal processor, where the object codes of the host processor and the signal processor are separately compiled, and the programmable signal processor has a memory for storing the signal processor object code and data, said apparatus comprising: a) high level programming means for defining processing tasks for the signal processor, said programming means including means for indicating host processor access to at least a portion of one of said processing tasks; and b) signal processor program compiling means coupled to said high level programing means for generating the signal processor object code which implements said processing tasks, and for generating a memory address list for the host processor, said memory address list indicating memory addresses corresponding to the host processor access to said tasks indicated by said high level programming means, said memory address list being read or received by a host processor compiling means.
Claim 30
Dependent Claim
29 words
Apparatus according to claim 25, wherein: said processing tasks include at least one function having a parameter and said host processor access includes supplying a value for said parameter.
Claim 31
Dependent Claim
29 words
Apparatus according to claim 25, wherein: said processing tasks include at least one function having an input and said host processor access includes supplying a value for said input.
Claim 32
Dependent Claim
40 words
Apparatus according to claim 26, wherein: said processing tasks include at least one function having an output and said host processor access includes reading said output and supplying said value of said parameter based on a value of said output.
Claim 33
Dependent Claim
40 words
Apparatus according to claim 27, wherein: said processing tasks include at least one function having an output and said host processor access includes reading said output and supplying said value of said input based on a value of said output.
Claim 34
Dependent Claim
11 words
An apparatus according to claim 25, further comprising: the host processor.
Claim 35
Dependent Claim
12 words
An apparatus according to claim 25, further comprising: the programmable signal processor.
Claim 36
Dependent Claim
16 words
An apparatus according to claim 25, further comprising: the host processor; and the programmable signal processor.
References Cited (Backward Citations)
US3815104A
Cited
US4193123A
Cited
US4231087A
Cited
US4414665A
Cited
US4315313A
Cited
US4467409A
Cited
US4464750A
Cited
US4410984A
Cited
US4371952A
Cited
US4435759A
Cited
US4439839A
Cited
US4626985A
Cited
US4611281A
Cited
US4581738A
Cited
US4608693A
Cited
US4750111A
Cited
US4604683A
Cited
US4641238A
Cited
US4860192A
Cited
US4674089A
Cited
US4967340A
Cited
US4748573A
Cited
US4873630A
Cited
US4788684A
Cited
US4740894A
Cited
US4783782A
Cited
US4677873A
Cited
US4835774A
Cited
US4888772A
Cited
US4868785A
Cited
US5151984A
Cited
US5042000A
Cited
US5068823A
Cited
US5031111A
Cited
US5031111C1
Cited
US4985830A
Cited
US4965718A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |