US4750111A
Expired / Lapsed
US
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Computer system for processing analog and digital data
Assignee: DUNN ROBERT T 4 CEDAR RIDGE DRIVE BEDFORD MA 01730
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Filing: 1984-08-22
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Granted: 1988-06-07
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Expires: 2004-08-22
Abstract
Abstract A computer system for processing analog and digital data input signals from many sources and producing analog and digital data output control signals includes a plurality of digital processing devices for processing the input data, a Processor Bus that interconnects the processing devices for relatively very high speed data transmission between the processing devices a plurality of analog and digital input and output data converter modules, a Converter Bus that interfaces the converter modules and a controller device that couples the Processor Bus and the Converter Bus together and controls the flow of signals therebetween, whereby analog and digital input data received at a range of data rates from relatively low to relatively high rates by input converter modules is transmitted on the Converter Bus to the Processor Bus, via the controller device, in digital format and is processed in the digital format at relatively very high data rates by one or more of the processing devices and digital output data from the processing devices is transmitted on the Processor Bus to the Converter Bus via the controller device and is converted by the converter modules which produce system outputs.
Inventors
- 👤 Edward D. Crosby, Jr.
- 👤 Stephen A. Marsh
- 👤 Larry A. Coates
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:06
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/368; G06F13/37; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06J; G06J1/00; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/027
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
332 words
A signal processing system for processing at relatively high digital signal rates a plurality of input signals from sources received at relatively low signal rates, and producing output signals for utilization devices comprising, (a) a plurality of input signal coverter modules for receiving and converting the system input signals into digital signals, herein called converted input signals, (b) a plurality of output signal converter modules for converting the system output signals for use by the utilization devices, (c) a synchronously operating converter module bus for said converter modules including one or more address lines, data lines, control lines and a clock line, to which said converter modules interface, (d) a plurality of digital signal processor devices that operate at relatively high digital signal rates, each adapted for generating, receiving and processing addresses, data, timing and control signals that are exchanged between said processor devices and each adapted for processing said converted input signals, (e) a synchronously operating processor device bus for said processor devices to which said processor devices interface, including a plurality of processor device address lines, data lines and timing and control lines for conducting addresses, data, timing and control signals, respectively, between said processor devices, (f) a source of processor bus clock signals, (g) means for coupling said processor bus clock signals to said processor bus timing line, (h) a source of converter bus clock signals, (i) means for coupling said converter bus clock signals to said converter bus clock line and (j) a converter bus controller device that interfaces to said processor bus and interfaces to said converter bus for controlling the flow of converted input signals from said converter modules to said processor devices, (k) whereby, the system accommodates relatively high-speed processing in said processor devices and between processor devices over said processor bus and relatively low-speed signal flow of converted input signals through said converter bus to said controller, while continually receiving input signals from said sources at said converter modules at relatively low signal rates.
Claim 2
Dependent Claim
332 words
A signal processing system for processing at relatively high digital signal rates a plurality of input signals from sources received at relatively low signal rates, and producing output signals for utilization devices comprising, (a) a plurality of input signal coverter modules for receiving and converting the system input signals into digital signals, herein called converted input signals, (b) a plurality of output signal converter modules for converting the system output signals for use by the utilization devices, (c) a synchronously operating converter module bus for said converter modules including one or more address lines, data lines, control lines and a clock line, to which said converter modules interface, (d) a plurality of digital signal processor devices that operate at relatively high digital signal rates, each adapted for generating, receiving and processing addresses, data, timing and control signals that are exchanged between said processor devices and each adapted for processing said converted input signals, (e) a synchronously operating processor device bus for said processor devices to which said processor devices interface, including a plurality of processor device address lines, data lines and timing and control lines for conducting addresses, data, timing and control signals, respectively, between said processor devices, (f) a source of processor bus clock signals, (g) means for coupling said processor bus clock signals to said processor bus timing line, (h) a source of converter bus clock signals, (i) means for coupling said converter bus clock signals to said converter bus clock line and (j) a converter bus controller device that interfaces to said processor bus and interfaces to said converter bus for controlling the flow of converted input signals from said converter modules to said processor devices, (k) whereby, the system accommodates relatively high-speed processing in said processor devices and between processor devices over said processor bus and relatively low-speed signal flow of converted input signals through said converter bus to said controller, while continually receiving input signals from said sources at said converter modules at relatively low signal rates.
Claim 3
Dependent Claim
73 words
A system as in claim 1 including more than one converter bus, like said converter bus, each with one or more converter modules, like said converter modules interfaced thereto and a converter bus controller device, like said converter bus controller device for each such converter bus that interfaces to said processor bus and interfaces to such converter bus for controlling signal flow of converted input signals from converter modules on said converter bus.
Claim 4
Dependent Claim
49 words
A system as in claim 1 including more than one processor bus, like said processor bus, each with one or more processor devices, like said processor devices, interfaced thereto and means for coupling said processor buses together so that the processor devices on different processor buses can exchange data.
Claim 5
Dependent Claim
49 words
A system as in claim 2 including more than one processor bus, like said processor bus, each with one or more processor devices, like said processor devices, interfaced thereto and means for coupling said processor buses together so that the processor devices on different processor buses can exchange data.
Claim 6
Dependent Claim
21 words
A system as in claim 3 wherein at least two of said processor buses receives clock signals from the same source.
Claim 7
Dependent Claim
21 words
A system as in claim 4 wherein at least two of said processor buses receive clock signals from the same source.
Claim 8
Dependent Claim
20 words
A system as in claim 3 wherein at least two of said processor buses have different sources of clock signals.
Claim 9
Dependent Claim
20 words
A system as in claim 4 wherein at least two of said processor buses have different sources of clock signals.
Claim 10
Dependent Claim
72 words
A system as in claim 1 for processing and producing output signals as well as input signals and further including, (a) one or more output signal converter modules that interface to said converter bus for converting data signals received over the converter bus from the processor devices to system output sigtnals and (b) said converter bus controller device controls the flow signals from the processor devices to said output signal converter modules.
Claim 11
Dependent Claim
19 words
A system as in claim 1 wherein an input and an output converter module are complementary to each other.
Claim 12
Dependent Claim
68 words
A system as in claim 1 and further including, (a) a test bus to which interface said complementary converter modules, (b) means coupled thereto for feeding the output of one of said complementary modules to the input of the other while comparing the input of the one to the output of the other, and (c) means for indicating a fault when the signals compared are not the same.
Claim 13
Dependent Claim
62 words
A system as in claim 1 wherein each of said processor devices includes interface circuits by which it interfaces to said processor bus, receives the clock signals, generates said address, data, timing and control signals and drives the same to the corresponding processor bus lines for transmission from it to the interface circuits of the other processor devices on said processor bus.
Claim 14
Dependent Claim
33 words
A system as in claim 12 wherein said timing signals include a processor bus cycle signal such that each processor bus cycle signal includes in integer number of processor bus clock pulse cycles.
Claim 15
Dependent Claim
73 words
A system as in claim 13 wherein said control signals includes: (a) a signal (PBREQ) signifying that the processor device generating PBREQ requires use of the processor bus during the current processor bus cycle as the master of the processor bus and (b) a signal (PBENO) during the bus cycle following the current processor bus cycle signifying that the processor device generating PBENO no longer requires to be master of the processor bus.
Claim 16
Dependent Claim
44 words
A system as in claim 14 wherein said interface circuits of each processor device includes: (a) means for receiving said signal PBREQ from other processor devices and (b) means for inhibiting its interface circuits from asserting its own PBREQ signal on the processor bus.
Claim 17
Dependent Claim
77 words
A system as in claim 15 wherein said interface circuits of each processor device includes: (a) means for signalling to the processor device that is next lower in priority to it a priority signal (PBENO) signifying that it is asserting PBREQ to the processor bus, (b) means for receiving a signal PBENO from the processor device that is next higher priority to it and (c) means responsive to said receiving means for inhibiting its assertion of PBREQ.
Claim 18
Dependent Claim
275 words
In a signal processing system for processing at relatively high digital signal rates a plurality of input signals from sources received at relatively low signal rates, and producing output signals for utilization devices at relatively low signal rates, the improvement comprising, (a) a plurality of input signal converter modules for receiving and converting the system input signals into digital signals, herein called converted input signals, (b) a plurality of output signal converter modules for converting the system output signals for use by the utilization devices, (c) a synchronously operating converter module bus for said converter modules to which said converter modules interface, (d) a plurality of digital signal processor devices that operate at relatively high digital signal rates (e) a synchronously operating processor devices bus for said processor devices to which said processor devices interface, (f) a source of relatively high rate processor bus clock signals, (g) means for coupling said processor bus clock signals to said processor bus, (h) a source of relatively lower rate converter bus clock signals, (i) means for coupling said converter bus clock signals to said converter bus and (j) a converter bus controller device that interfaces to said processor bus and interfaces to said converter bus for controlling the flow of converted input signals from said input converter modules to said processor devices and for controlling the flow of said output signals to said output converter modules, (k) whereby, the system accommodates relatively high-speed processing in said processor devices and between processor devices over said processor bus and relatively low-speed signal flow of converted input signals from said input converter modules and output signals to said output converter modules.
Claim 19
Dependent Claim
275 words
In a signal processing system for processing at relatively high digital signal rates a plurality of input signals from sources received at relatively low signal rates, and producing output signals for utilization devices at relatively low signal rates, the improvement comprising, (a) a plurality of input signal converter modules for receiving and converting the system input signals into digital signals, herein called converted input signals, (b) a plurality of output signal converter modules for converting the system output signals for use by the utilization devices, (c) a synchronously operating converter module bus for said converter modules to which said converter modules interface, (d) a plurality of digital signal processor devices that operate at relatively high digital signal rates (e) a synchronously operating processor devices bus for said processor devices to which said processor devices interface, (f) a source of relatively high rate processor bus clock signals, (g) means for coupling said processor bus clock signals to said processor bus, (h) a source of relatively lower rate converter bus clock signals, (i) means for coupling said converter bus clock signals to said converter bus and (j) a converter bus controller device that interfaces to said processor bus and interfaces to said converter bus for controlling the flow of converted input signals from said input converter modules to said processor devices and for controlling the flow of said output signals to said output converter modules, (k) whereby, the system accommodates relatively high-speed processing in said processor devices and between processor devices over said processor bus and relatively low-speed signal flow of converted input signals from said input converter modules and output signals to said output converter modules.
Claim 20
Dependent Claim
73 words
A system as in claim 17 including more than one converter bus, like said converter bus, each with one or more converter modules, like said converter modules interfaced thereto and a converter bus controller device, like said converter bus controller device for each such converter bus that interfaces to the processor bus and interfaces to such converter bus for controlling signal flow of converted input signals from converter modules on said converter bus.
Claim 21
Dependent Claim
49 words
A system as in claim 17 including more than one processor bus, like said processor bus, each with one or more processor devices, like said processor devices, interfaced thereto and means for coupling said processor buses together so that the processor devices on different processor buses can exchange data.
Claim 22
Dependent Claim
49 words
A system as in claim 18 including more than one processor bus, like said processor bus, each with one or more processor devices, like said processor devices, interfaced thereto and means for coupling said processor buses together so that the processor devices on different processor buses can exchange data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-06-07 | 1991-12-07 | 1992-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-06-07 | 1995-12-07 | 1996-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-06-07 | 1999-12-07 | 2000-06-07 | $7700.00 | Window Closed / Lapsed |