Microprocessor support system

Claim 2

A processor support system for providing maintenance and software development for an application system which is controlled by an application processor via data, address, and control buses, wherein said processor support system comprises: computer means for running an operating system to generate and store software for said application system; field test unit means connected between said computer means and said application system for interfacing said computer means with said application system, wherein said field test unit means comprises: program store means for storing control instructions generated by said computer means for regulating the operation of said field test unit means; processor means for controlling the operation of said application system; memory means for storing said software generated by said computer means and written in said memory means by said computer means; interface means responsive to said processor means and directly connectable to said application system data, address, and control buses for connecting said application processor to said memory means; field test unit bus means connected to said program store means and to said processor means for applying said control instructions to said processor means; and wherein said processor means is responsive to said control instructions for directing said application processor via said interface means to execute said software stored in said memory means.

Claim 3

The invention of claim 1 wherein said field test unit means includes: terminal means for providing an engineer with data access to said processor support system; access means for transmitting input data from said terminal means on said data link to said computer means; and wherein said computer means are responsive to said input data to generate application software for said application system.

Claim 4

The invention of claim 1 wherein said interface means includes: supervision means responsive to said processor means and connected to said application system data, address, and control bus for monitoring and driving said application system data, address, and control bus.

Claim 5

The invention of claim 3 wherein said supervision means includes transfer trace means connected to said interface means and responsive to signals appearing on said application system data, address, and control bus for storing data representative of the program branches taken by said application processor in the execution of said application software.

Claim 6

The invention of claim 3 wherein said supervision means includes: matcher means connected to said field test unit data, address, and control bus means and responsive to programming signals applied to said field test unit data, address, and control bus means by said processor means for storing said programming signals; and wherein said matcher means are connected to said interface means and are responsive to signals appearing on said application system data bus for generating a match indication signal whenever said signals appearing on said application system data are identical to said programming signals stored in said matcher means.

Claim 7

The invention of claim 5 wherein said matcher means includes Nth pass counter means responsive to said programming signals for storing a count indication; wherein said matcher means decrements said count indication stored in said Nth pass counter means whenever said signals appearing on said application system data bus are identical to said programming signals stored in said matcher means; and wherein said matcher means generates an Nth pass match indication signal when said count indication stored in said Nth pass counter means equals zero.

Claim 8

The invention of claim 6 wherein said supervision means includes: elapsed time clock means responsive to said match indication signal for indicating the amount of real time elapsed between subsequent appearances of said match indication signal.

Claim 9

The invention of claim 3 wherein said supervision means includes: buffer means connected to said application system data, address, and control buses for transmitting all signals appearing on said application system data, address, and control buses to said access means; and wherein said access means is additionally responsive to said buffer means for transmitting said signals appearing on said application system data, address, and control buses to said computer means via said data link for storage.

Claim 10

The invention of claim 1 wherein said computer means includes a time-shared computer connectable to a plurality of field test unit means.

Claim 11

The invention of claim 9 wherein said computer means is remotely located from said application system and said field test unit means; and wherein said access means comprises a data modem.

Claim 12

A processor support system for providing hardware debugging and software development capabilities for an application system which contains both a memory device and an application processor which processor drives data, address, and control buses of said application system, wherein said microprocessor support system comprises: computer means responsive to control signals input from a user terminal for running an operating system to generate control instructions and to manipulate data; field test unit means connected to said computer means by a data link and directly connected to said application system for ordering the flow of said data between said computer means and said application system; wherein said field test unit means includes: field test unit data, address, and control bus means for interconnecting the various circuits of said field test unit means; program store means connected to said field test unit data, address, and control bus means for storing said control instructions generated by said computer means to regulate the operation of said field test unit means; data receiver means connected to both said data link and said field test unit data, address, and control bus means, wherein said data receiver means are responsive to said computer means transmitting said control instructions to said field test unit means via said data link for writing said control instructions into said program store means via said field test unit data, address, and control bus means; processor means connected to said field test unit data, address, and control bus means and responsive to said control instructions stored in said program store means for driving said field test unit data, address, and control bus means; memory means connected to said field test unit data, address, and control bus means for storing data generated by said application system; interface means connected to said field test unit data, address, and control bus means and directly connectable to said application system data, address, and control buses for providing bidirectional data transfer between said application system data, address, and control buses and said memory means via said field test unit data, address, and control bus means in response to control signals transmitted to said processor means to said interface means via said field test unit data, address, and control bus means; and data transmission means connected to both said data link and said field test unit data, address, and control bus means and responsive to said processor means for transmitting said data from said memory means to said computer via said data link.

Claim 13

A processor support system for providing hardware debugging and software development capabilities for an application system which contains both a memory device and an application processor which processor drives data, address, and control buses of said application system, wherein said microprocessor support system comprises: computer means responsive to control signals input from a user terminal for running an operating system to generate control instructions and to manipulate data; field test unit means connected to said computer means by a data link and directly connected to said application system for ordering the flow of said data between said computer means and said application system; wherein said field test unit means includes: field test unit data, address, and control bus means for interconnecting the various circuits of said field test unit means; program store means connected to said field test unit data, address, and control bus means for storing said control instructions generated by said computer means to regulate the operation of said field test unit means; data receiver means connected to both said data link and said field test unit data, address, and control bus means, wherein said data receiver means are responsive to said computer means transmitting said control instructions to said field test unit means via said data link for writing said control instructions into said program store means via said field test unit data, address, and control bus means; processor means connected to said field test unit data, address, and control bus means and responsive to said control instructions stored in said program store means for driving said field test unit data, address, and control bus means; memory means connected to said field test unit data, address, and control bus means for storing data generated by said application system; interface means connected to said field test unit data, address, and control bus means and directly connectable to said application system data, address, and control buses for providing bidirectional data transfer between said application system data, address, and control buses and said memory means via said field test unit data, address, and control bus means in response to control signals transmitted to said processor means to said interface means via said field test unit data, address, and control bus means; and data transmission means connected to both said data link and said field test unit data, address, and control bus means and responsive to said processor means for transmitting said data from said memory means to said computer via said data link.

Claim 14

The invention of claim 11 wherein said field test unit means includes transceiver means responsive to said processor means for transmitting data stored in said memory means to said computer means via said data link and for receiving data transmitted by said computer means via said data link.

Claim 15

The invention of claim 12 wherein said field test unit means includes: terminal means for providing an engineer with data access to said field test unit; and input means connected to said field test unit data, address, and control bus means and responsive to input data entered into said terminal means for storing said input data in said memory means.

Claim 16

The invention of claim 11 wherein said processor means is responsive to said control instructions for concurrently enabling the transfer of data between said interface means and said memory means and between said memory means and said computer means.

Claim 17

The invention of claim 11 wherein said interface means is responsive to said processor means for reading the contents of said application system memory onto said field test unit address, data, and control bus means.

Claim 18

The invention of claim 15 wherein said processor means is additionally responsive to said control instructions for regulating the operation of said application processor by driving said control bus of said application processor via said interface means.

Claim 19

The invention of claim 15 wherein said field test unit means includes buffer means for connecting said field test unit data, address, and control bus means to said transceiver means for transmitting said contents of said application system memory appearing on said field test unit data, address and control bus means to said computer means via said data link.

Claim 20

The invention of claim 16 wherein said interface means is responsive to said processor means for halting the operation of said application processor.