US4084233A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microcomputer apparatus
Assignee: Honeywell Inc
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Filing: 1976-05-25
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Granted: 1978-04-11
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Expires: 1996-05-25
Abstract
Abstract A computer system features a processor unit which includes its own microprogram control unit. The microprogram control unit includes a storage means for operational instructions for the processor unit and means to issue those instructions in a desired sequence. A communication Bus provides communication channels between the processor unit and either data storage means or other processor units served by the Bus. The processor unit includes a number of clock controlled functional components as well as means for requesting access to the Bus. A clock signal generating means is controlled by signals from the microprogram control unit. When a request has been made for access to the Bus, the processor continues to operate until a point is reached when access to the Bus must be accomplished before continuing. The microprogram control unit issues a control signal which effectively stops the operation of the clock signal generating means until the Bus access routine has been accomplished. The clock signal generating means resumes operation when the access routine has been completed.
Inventors
- 👤 Robert J. Handly
- 👤 Robert H. Douglas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 22:17
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F13/00; G06F13/14; G06F13/36; G06F13/362
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
88 words
In a computer system, a processing unit including, a plurality of functional components, a microprogram control unit, said microprogram control unit including storage means for storing operational instructions for said processing unit and means to issue said operational instructions in a desired sequence, said plurality of functional components being controlled by said microprogram control unit, clock means for clocking the operation of said components and said microprogram control unit, and means responsive to a first and a second control signal for interrupting the operation of said clock means.
Claim 2
Dependent Claim
88 words
In a computer system, a processing unit including, a plurality of functional components, a microprogram control unit, said microprogram control unit including storage means for storing operational instructions for said processing unit and means to issue said operational instructions in a desired sequence, said plurality of functional components being controlled by said microprogram control unit, clock means for clocking the operation of said components and said microprogram control unit, and means responsive to a first and a second control signal for interrupting the operation of said clock means.
Claim 3
Dependent Claim
147 words
In a computer system, a processing unit, a data storage unit, a communication Bus for selectively providing communication channels between said processing unit and said storage unit, a Bus controller for controlling access to said Bus by said processing unit, said processing unit including a plurality of functional components and a microprogram control unit, said microprogram control unit including storage means for storing operational control instructions for said processing unit and means to issue said operational instructions in a desired sequence, said plurality of functional components being controlled by said microprogram control unit, said processing unit further including a clock means for clocking the operation of said functional components and said microprogram control unit, and means responsive to the coincidence of a first control signal from said microprogram control unit and a second control signal from said Bus controller to interrupt the operation of said clock means.
Claim 4
Dependent Claim
147 words
In a computer system, a processing unit, a data storage unit, a communication Bus for selectively providing communication channels between said processing unit and said storage unit, a Bus controller for controlling access to said Bus by said processing unit, said processing unit including a plurality of functional components and a microprogram control unit, said microprogram control unit including storage means for storing operational control instructions for said processing unit and means to issue said operational instructions in a desired sequence, said plurality of functional components being controlled by said microprogram control unit, said processing unit further including a clock means for clocking the operation of said functional components and said microprogram control unit, and means responsive to the coincidence of a first control signal from said microprogram control unit and a second control signal from said Bus controller to interrupt the operation of said clock means.
Claim 5
Dependent Claim
156 words
In a computer system, a processing unit, a storage unit, a communication Bus for selectively providing communication channels between said processing unit and said storage unit, a Bus controller for controlling access to said Bus by said processing unit, said processing unit including a plurality of functional components and a microprogram control unit, said microprogram control unit including storage means for storing operational control instructions for said processing unit and means to issue said operational instructions in a desired sequence, said plurality of functional components being controlled by said microprogram control unit, said processing unit further including a clock means for clocking the operation of said functional components and said microprogram control unit, said clock circuit comprising an interruptible, free-running solid state oscillator, and means responsive to the coincidence of a first control signal from said microprogram control unit and a second control signal from said Bus controller to interrupt the operation of said clock means.
Claim 6
Dependent Claim
156 words
In a computer system, a processing unit, a storage unit, a communication Bus for selectively providing communication channels between said processing unit and said storage unit, a Bus controller for controlling access to said Bus by said processing unit, said processing unit including a plurality of functional components and a microprogram control unit, said microprogram control unit including storage means for storing operational control instructions for said processing unit and means to issue said operational instructions in a desired sequence, said plurality of functional components being controlled by said microprogram control unit, said processing unit further including a clock means for clocking the operation of said functional components and said microprogram control unit, said clock circuit comprising an interruptible, free-running solid state oscillator, and means responsive to the coincidence of a first control signal from said microprogram control unit and a second control signal from said Bus controller to interrupt the operation of said clock means.
Claim 7
Dependent Claim
103 words
The computer system as set forth in claim 3 wherein said clock means comprises a first solid-state gate means having two input terminals and an output terminal, a signal delay means connected between said output terminal and one of said input terminals, an enabling circuit comprising a second solid-state gate means having an output terminal connected to the other input terminal of said first gate means, said second gate means having a first input terminal connected to receive said first control signal from said microprogram control unit and a second input terminal connected to receive said second control signal from said Bus controller.
Claim 8
Dependent Claim
197 words
In a computer system, a processing unit, a storage unit, a communication Bus for selectively providing communication channels between processing units and said storage unit, a Bus controller for controlling access to said Bus by said storage unit, said processing unit including a plurality of functional components and a microprogram control unit, said microprogram control unit including storage means for storing operational control instructions for said processing unit and means to issue said operational instructions in a desired sequence, said plurality of functional components being controlled by said microprogram control unit, said processing unit further including a clock circuit for clocking the operation of said functional components and said microprogram control unit, said clock circuit comprising an interruptible, free-running solid state oscillator, and means responsive to the coincidence of a first control signal from said microprogram control unit comprising a WAIT signal effective before the completion of each instruction and a second control signal from said Bus controller indicative that a require access to the Bus has not been completed, said coincidence of said first and second control signal being effective to interrupt the operation of said clock circuit until said required Bus access has been completed.
Claim 9
Dependent Claim
197 words
In a computer system, a processing unit, a storage unit, a communication Bus for selectively providing communication channels between processing units and said storage unit, a Bus controller for controlling access to said Bus by said storage unit, said processing unit including a plurality of functional components and a microprogram control unit, said microprogram control unit including storage means for storing operational control instructions for said processing unit and means to issue said operational instructions in a desired sequence, said plurality of functional components being controlled by said microprogram control unit, said processing unit further including a clock circuit for clocking the operation of said functional components and said microprogram control unit, said clock circuit comprising an interruptible, free-running solid state oscillator, and means responsive to the coincidence of a first control signal from said microprogram control unit comprising a WAIT signal effective before the completion of each instruction and a second control signal from said Bus controller indicative that a require access to the Bus has not been completed, said coincidence of said first and second control signal being effective to interrupt the operation of said clock circuit until said required Bus access has been completed.
Claim 10
Dependent Claim
163 words
In a computer system, a plurality of processing units, at least one data storage unit, a communication Bus for selectively providing communication channels between said processing units and said storage unit and between processing units, a Bus controller for controlling access to said Bus by said processing units, at least one of said processing units including a plurality of functional components and a microprogram control unit, said microprogram control unit including storage means for storing operational instructions for said processing unit and means to issue said operational instructions in a desired sequence, said plurality of functional components being controlled by said microprogram control unit, said at least one of said processing units further including a clock means for clocking the operation of said functional components and said microprogram control unit, and means responsive to the coincidence of a first control signal from said microprogram control unit and a second control signal from said Bus controller to interrupt the operation of said clock means.
Claim 11
Dependent Claim
163 words
In a computer system, a plurality of processing units, at least one data storage unit, a communication Bus for selectively providing communication channels between said processing units and said storage unit and between processing units, a Bus controller for controlling access to said Bus by said processing units, at least one of said processing units including a plurality of functional components and a microprogram control unit, said microprogram control unit including storage means for storing operational instructions for said processing unit and means to issue said operational instructions in a desired sequence, said plurality of functional components being controlled by said microprogram control unit, said at least one of said processing units further including a clock means for clocking the operation of said functional components and said microprogram control unit, and means responsive to the coincidence of a first control signal from said microprogram control unit and a second control signal from said Bus controller to interrupt the operation of said clock means.
Claim 12
Dependent Claim
117 words
A clock circuit for a computational unit, said clock circuit comprising an interruptible, free-running solid-state oscillator and including, a first solid-state gate means having two input terminals and an output terminal, a signal delay means connected between said output terminal and one of said input terminals, an enabling circuit comprising a second solid-state gate means having two input terminals and an output terminal, the output terminal of said second gate means being connected to the second one of the two terminals of said first gate means, said two input terminals of said second gate means being arranged to receive a first and a second control signal, respectively, coincidence of which is effective to disable said clock circuit.
Claim 13
Dependent Claim
117 words
A clock circuit for a computational unit, said clock circuit comprising an interruptible, free-running solid-state oscillator and including, a first solid-state gate means having two input terminals and an output terminal, a signal delay means connected between said output terminal and one of said input terminals, an enabling circuit comprising a second solid-state gate means having two input terminals and an output terminal, the output terminal of said second gate means being connected to the second one of the two terminals of said first gate means, said two input terminals of said second gate means being arranged to receive a first and a second control signal, respectively, coincidence of which is effective to disable said clock circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-10 | 1981-10-10 | 1982-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-10 | 1985-10-10 | 1986-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-10 | 1989-10-10 | 1990-04-11 | $7700.00 | Window Closed / Lapsed |