Patent US20050137601A1 successfully refreshed from Google Patents.
US4788684A
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Memory test apparatus
Assignee: Hitachi Ltd
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Filing: 1986-08-12
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Granted: 1988-11-29
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Expires: 2006-08-12
Abstract
Abstract A memory test apparatus for testing a high-performance memory having two or more memory functions, including a pattern generator for generating an algorithmic pattern to be inputted to a first memory block of a memory under test having at least two memory blocks, an auxiliary pattern generator for storing an output from the algorithmic pattern generator and for outputting an expected value to a second memory block of the memory under test at a preset timing based on the stored output, a comparator for comparing outputs from the first and second memory blocks with expected values for the memory blocks, and a memory for storing an output from the comparator. Since the algorithmic pattern generator and the auxiliary pattern generator are included, the test apparatus has such an affect that even if the first and second memory blocks of the memory under test operate asynchronously, the data transfer function therebetween and the performance related to the operation timing can be tested, thus providing a highly precise memory test apparatus.
Inventors
- 👤 Ikuo Kawaguchi
- 👤 Yoshihiko Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:09
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
112 words
A memory test apparatus for testing a high performance memory of the type having first and second memory blocks, comprising: means for generating an algorithmic pattern to be inputted to a first block of a memory under test; auxiliary pattern generating means for storing an output from said algorithmic pattern generating means and for outputting an expected value for a second block of the memory under test at a preset timing based on the stored output; means for comparing outputs from said first and second blocks of the memory under test with expected values for said first and second blocks, respectively; and memory means for storing an output from said comparing means.
Claim 2
Dependent Claim
112 words
A memory test apparatus for testing a high performance memory of the type having first and second memory blocks, comprising: means for generating an algorithmic pattern to be inputted to a first block of a memory under test; auxiliary pattern generating means for storing an output from said algorithmic pattern generating means and for outputting an expected value for a second block of the memory under test at a preset timing based on the stored output; means for comparing outputs from said first and second blocks of the memory under test with expected values for said first and second blocks, respectively; and memory means for storing an output from said comparing means.
Claim 3
Dependent Claim
51 words
A memory test apparatus according to claim 1, wherein said auxiliary pattern generating means contains a content equal to a content of said first block of the memory under test and outputs as an expected value a pattern identical to a pattern transferred from said first block to said second block.
Claim 4
Dependent Claim
20 words
A memory test apparatus according to claim 1, wherein said second block of the test memory is a shift register.
Claim 5
Dependent Claim
41 words
A memory test apparatus according to claim 1, wherein said auxiliary pattern generating means receives an address signal and input data outputted from said algorithmic pattern generating means and includes a plurality of pattern memory units for storing the input data.
Claim 6
Dependent Claim
22 words
A memory test apparatus according to claim 4, wherein said address signal comprises an X address signal and a Y address signal.
Claim 7
Dependent Claim
74 words
A memory test apparatus according to claim 1, wherein said auxiliary pattern generating means receives an address signal and input data outputted from said algorithmic pattern generate means, outputs a fail memory address signal to a memory in which the output from said comparing means is stored, and outputs a generation completion signal indicating a completion of generation of a series of expected values for said second block to said algorithmic pattern generate means.
Claim 8
Dependent Claim
166 words
A memory test apparatus for testing a higher performance memory of the type having first and second memory block, comprising: means for generating an algorithmic pattern to be inputted to a first block of a memory under test; auxiliary pattern generating means for storing an output from said algorithmic pattern generating means and for outputting an expected value for a second block of the memory under test with expected values for said first and second blocks, respectively; means for comparing outputs from said first and second blocks of the memory with expected values for said first and second blocks, respectively; memory means for storing an output from said comparing means; master timing generating means for outputting a clock used to test said first block to said algorithmic pattern generating means; and slave phase signal to test said second block to said auxiliary pattern generating means; slave timing generate mean for outputting a slave phase signal to test said second block to said auxiliary pattern generate means.
Claim 9
Dependent Claim
166 words
A memory test apparatus for testing a higher performance memory of the type having first and second memory block, comprising: means for generating an algorithmic pattern to be inputted to a first block of a memory under test; auxiliary pattern generating means for storing an output from said algorithmic pattern generating means and for outputting an expected value for a second block of the memory under test with expected values for said first and second blocks, respectively; means for comparing outputs from said first and second blocks of the memory with expected values for said first and second blocks, respectively; memory means for storing an output from said comparing means; master timing generating means for outputting a clock used to test said first block to said algorithmic pattern generating means; and slave phase signal to test said second block to said auxiliary pattern generating means; slave timing generate mean for outputting a slave phase signal to test said second block to said auxiliary pattern generate means.
Claim 10
Dependent Claim
51 words
A memory test apparatus according to claim 7, wherein said auxiliary pattern generating means contains a content equal to a content of said first block of the memory under test and outputs as an expected value a pattern identical to a pattern transferred from said first block to said second block.
Claim 11
Dependent Claim
19 words
A memory test apparatus according to claim 7, wherein said second block of the memory is a shift register.
Claim 12
Dependent Claim
42 words
A memory test apparatus according to claim 7, wherein said auxiliary pattern generating means receives an address signal and an input data outputted from said algorithmic pattern generating means and includes a plurality of pattern memory units for storing the input data.
Claim 13
Dependent Claim
22 words
A memory test apparatus according to claim 10, wherein said address signal comprises an X address signal and a Y address signal.
Claim 14
Dependent Claim
75 words
A memory test apparatus according to claim 7, wherein said auxiliary pattern generating means receives an address signal and an input data outputted from said algorithmic pattern generating means, outputs a fail memory address signal to a memory in which the output from said comparing means is stored, and outputs a generation completion signal indicating a completion of generation of a series of expected values for said second block to said algorithmic pattern generating means.
Claim 15
Dependent Claim
48 words
A memory test apparatus according to claim 7, wherein said master timing generating means comprises: a test cycle counter and a phase counter each for receiving a basic clock from an oscillator and a latch for receiving a timing select signal outputted from said algorithmic pattern generating means.
Claim 16
Dependent Claim
47 words
A memory test means according to claim 7, wherein said slave timing generating means comprises: a phase counter for receiving a basic clock from an oscillator and an OR gate and a flip-flop circuit each for receiving a slave control signal from said master timing generating means.
Claim 17
Dependent Claim
54 words
A memory test apparatus according to claim 7 further comprising at least a second slave timing generating means in addition to said slave timing generating means wherein: slave control signals from said master timing generating means are inputted to said slave timing generating means and said at least a second slave timing generating means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-29 | 1992-05-30 | 1992-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-29 | 1996-05-30 | 1996-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-29 | 2000-05-30 | 2000-11-29 | $7700.00 | Window Closed / Lapsed |