US4626985A
Expired / Lapsed
US
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Single-chip microcomputer with internal time-multiplexed address/data/interrupt bus
Assignee: STMicroelectronics lnc USA
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Filing: 1985-10-03
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Granted: 1986-12-02
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Expires: 2005-10-03
Abstract
Abstract A microcomputer architecture permits communication between a CPU and same-chip ports and input/output circuits to be carried only over a multiplexed address/data/interrupt bus, thereby permitting modified I/O hardware or other circuits to be included in the microcomputer without disturbing the CPU layout.
Inventors
- 👤 Willard S. Briggs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:01
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F15/00; G06F15/76; G06F15/78; G06F15/7807; G06F15/7814
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
220 words
A single-chip microcomputer having on-chip memory and a number of logical units on an integrated circuit chip, including: a first processing unit; at least one on-chip input/output unit; at least one port register unit external to said first processing unit; at least one memory unit; means for passing interrupt flag signals from at least one interrupt source to said first processing unit; and means for passing signals to and from said logical units and said processing unit along at least one time-multiplexed internal address/data bus; in which microcomputer said input/output unit, port register unit and memory unit are all mapped in a memory space, each having at least one memory address in said memory space; characterized in that: said means for passing signals includes means for time-multiplexing, within an instruction cycle, said internal address/data bus between an interrupt-sensing period and at least one other period, whereby said internal address/data bus becomes an address/data/interrupt bus; said first processing unit includes means for sensing interrupt flag signals indicating the presence of interrupt on said internal address/data bus during said interrupt-sensing period; and said internal address/data bus is the only signal path for address data, non-address data and interrupt flag signals between said first processing unit and any of said at least one on-chip input/output unit and said at least one port register.
Claim 2
Dependent Claim
220 words
A single-chip microcomputer having on-chip memory and a number of logical units on an integrated circuit chip, including: a first processing unit; at least one on-chip input/output unit; at least one port register unit external to said first processing unit; at least one memory unit; means for passing interrupt flag signals from at least one interrupt source to said first processing unit; and means for passing signals to and from said logical units and said processing unit along at least one time-multiplexed internal address/data bus; in which microcomputer said input/output unit, port register unit and memory unit are all mapped in a memory space, each having at least one memory address in said memory space; characterized in that: said means for passing signals includes means for time-multiplexing, within an instruction cycle, said internal address/data bus between an interrupt-sensing period and at least one other period, whereby said internal address/data bus becomes an address/data/interrupt bus; said first processing unit includes means for sensing interrupt flag signals indicating the presence of interrupt on said internal address/data bus during said interrupt-sensing period; and said internal address/data bus is the only signal path for address data, non-address data and interrupt flag signals between said first processing unit and any of said at least one on-chip input/output unit and said at least one port register.
Claim 3
Dependent Claim
54 words
A microcomputer according to claim 1, further characterized in that said first processing unit transmits memory addresses to said on-chip memory unit on a memory bus separate from said multiplexed address/data/interrupt bus and in which non-address data passes between said on-chip memory unit and said first processing unit on said time-multiplexed internal address/data/interrupt bus.
Claim 4
Dependent Claim
265 words
A microcomputer having on-chip memory and a number of logical units on an integrated circuit chip, including: a first processing unit; at least one on-chip input/output unit; at least one port register unit external to said first processing unit; at least one memory unit; means for passing interrupt flag signals from at least one interrupt source to said first processing unit; and means for passing signals to and from said logical units and said processing unit along at least one time-multiplexed internal address/data bus; in which microcomputer said input/output unit, port register unit and memory unit are all mapped in a memory space, each having at least one memory address in said memory space; characterized in that: said means for passing signals includes means for time-multiplexing, within an instruction cycle, said internal address/data bus between an interrupt-sensing period and at least one other period, whereby said internal address/data bus becomes an address/data/interrupt bus; said first processing unit includes means for sensing interrupt flag signals indicating the presence of an interrupt on said internal address/data bus during said interrupt-sensing period, whereby said internal address/data bus becomes an address/data/interrupt bus; said internal address/data bus is the only signal path for address data, non-address data and interrupt flag signals between said first processing unit and any of said at least one on-chip input/output unit and said at least one port register; and at least two interrupt sources each have a reserved line on said internal bus, whereby at least two interrupt flag signals may pass simultaneously from said at least two interrupt sources into said first processing unit.
Claim 5
Dependent Claim
265 words
A microcomputer having on-chip memory and a number of logical units on an integrated circuit chip, including: a first processing unit; at least one on-chip input/output unit; at least one port register unit external to said first processing unit; at least one memory unit; means for passing interrupt flag signals from at least one interrupt source to said first processing unit; and means for passing signals to and from said logical units and said processing unit along at least one time-multiplexed internal address/data bus; in which microcomputer said input/output unit, port register unit and memory unit are all mapped in a memory space, each having at least one memory address in said memory space; characterized in that: said means for passing signals includes means for time-multiplexing, within an instruction cycle, said internal address/data bus between an interrupt-sensing period and at least one other period, whereby said internal address/data bus becomes an address/data/interrupt bus; said first processing unit includes means for sensing interrupt flag signals indicating the presence of an interrupt on said internal address/data bus during said interrupt-sensing period, whereby said internal address/data bus becomes an address/data/interrupt bus; said internal address/data bus is the only signal path for address data, non-address data and interrupt flag signals between said first processing unit and any of said at least one on-chip input/output unit and said at least one port register; and at least two interrupt sources each have a reserved line on said internal bus, whereby at least two interrupt flag signals may pass simultaneously from said at least two interrupt sources into said first processing unit.
Claim 6
Dependent Claim
50 words
A microcomputer according to claim 3, further characterized in that said at least two interrupt flag signals pass into programmable priority means in said first processing unit, whereby the response of said first processing unit to an interrupt may be altered during real time by a program in said microcomputer.
Claim 7
Dependent Claim
55 words
A microcomputer according to claim 3, further characterized in that said first processing unit transmits memory addresses to said on-chip memory unit on a memory bus separate from said multiplexed address/data/interrupt bus and in which non-address data passes between said on-chip memory unit and said first processing unit on said time multiplexed internal address/data/interrupt bus.
Claim 8
Dependent Claim
20 words
A microcomputer according to claim 3, further characterized in that said reserved lines are time-multiplexed lines in said time-multiplexed bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-01 | 1990-06-02 | 1990-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-01 | 1994-06-02 | 1994-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-01 | 1998-06-02 | 1998-12-02 | $7700.00 | Window Closed / Lapsed |