Priority interrupt system for microcomputer

Claim 2

A priority interrupt system for a microcomputer having a program read only memory for storing service routines for servicing a plurality of peripheral devices, comprising: program counter means for stepping through the addresses of the program read only memory in the microcomputer; input means for receiving interrupt request signals from the peripheral devices indicating requests for access to the microcomputer; read only memory means for storing interrupt address jump vectors corresponding to the service routines for servicing the peripheral devices; priority encoder means responsive to said input means for producing priority signals to select interrupt address jump vectors from said read only memory means in accordance with a predetermined priority basis in response to the interrupt request signals from the peripheral devices; control means responsive to said input means for transferring the contents of said program counter means into the microcomputer memory upon occurrence of an interrupt signal; loading means responsive to said control means for loading the interrupt address jump vectors from said read only memory means into said program counter means to allow the microcomputer to immediately service the peripheral device requesting access to the computer; said input means further comprising: a first set of storage devices corresponding in number to the number of peripheral devices, for receiving and storing the interrupt request signals directly from different peripheral devices, and a means for latching at any selected time all said storage devices to store therein all the interrupt request signals present at said first set of storage devices while the corresponding interrupt address jump vectors are loaded in priority sequence into said program counter means to allow the peripheral devices requesting access to be serviced on the predetermined priority basis.

Claim 3

A priority interrupt system for a microcomputer having a program read only memory for storing service routines for servicing a plurality of peripheral devices, comprising: program counter means for stepping through the addresses of the program read only memory in the microcomputer; input means for receiving interrupt request signals from the peripheral devices indicating requests for access to the microcomputer, said input means including a first set of storage devices corresponding in number to the number of peripheral devices and adapted to being coupled to a second set of storage devices for actuating a control means in response to an interrupt request signal; and enabling means coupling said first set of storage devices to a second set of storage devices to selectively enable and disable the transfer of the interrupt request signals from the first set of storage devices to said second set of storage devices; read only memory means for storing interrupt address jump vectors corresponding to the service routines for servicing the peripheral devices; priority encoder means responsive to said input means for producing priority signals to select interrupt address jump vectors from said read only memory means in accordance with a predetermined priority basis in response to the interrupt request signals from the peripheral devices; control means responsive to said input means for transferring the contents of said program counter means into the microcomputer memory upon occurrence of an interrupt signal; loading means responsive to said control means for loading the interrupt address jump vectors from said read only memory means into said program counter means to allow the microcomputer to immediately service the peripheral device requesting access to the computer; a second set of storage devices corresponding in number to the number of peripheral devices coupled to said enabling means and responsive to the interrupt request signals from different peripheral devices; and means for latching at any selected time said sets of storage devices to store the interrupt request signals therein while the corresponding interrupt address jump vectors are loaded in sequence into said program counter means to allow the peripheral devices requesting access to be serviced on the predetermined priority basis.

Claim 4

A priority interrupt system for a microcomputer having a program read only memory for storing service routines for servicing a plurality of peripheral devices, comprising: program counter means for stepping through the addresses of the program read only memory in the microcomputer; input means for receiving interrupt request signals from the peripheral devices indicating requests for access to the microcomputer, said input means including a first set of storage devices corresponding in number to the number of peripheral devices and adapted to being coupled to a second set of storage devices for actuating a control means in response to an interrupt request signal; and enabling means coupling said first set of storage devices to a second set of storage devices to selectively enable and disable the transfer of the interrupt request signals from the first set of storage devices to said second set of storage devices; read only memory means for storing interrupt address jump vectors corresponding to the service routines for servicing the peripheral devices; priority encoder means responsive to said input means for producing priority signals to select interrupt address jump vectors from said read only memory means in accordance with a predetermined priority basis in response to the interrupt request signals from the peripheral devices; control means responsive to said input means for transferring the contents of said program counter means into the microcomputer memory upon occurrence of an interrupt signal; loading means responsive to said control means for loading the interrupt address jump vectors from said read only memory means into said program counter means to allow the microcomputer to immediately service the peripheral device requesting access to the computer; a second set of storage devices corresponding in number to the number of peripheral devices coupled to said enabling means and responsive to the interrupt request signals from different peripheral devices; and means for latching at any selected time said sets of storage devices to store the interrupt request signals therein while the corresponding interrupt address jump vectors are loaded in sequence into said program counter means to allow the peripheral devices requesting access to be serviced on the predetermined priority basis.

Claim 5

A priority interrupt system for a microcomputer having a program read only memory for storing service routines for servicing a plurality of peripheral devices, comprising: program counter means for stepping through the addresses of the program read-only memory in the microcomputer; input means for receiving interrupt request signals from the peripheral devices indicating requests for access to the microcomputer, said input means including a first set of storage devices corresponding in number to the number of peripheral devices and adapted to being coupled to a second set of storage devices for actuating a control means in response to an interrupt request signal; and enabling means coupling said first set of storage devices to a second set of storage devices to selectively enable and disable the transfer of the interrupt request signals from the first set of storage devices to said second set of storage devices: read-only memory means for storing interrupt address jump vectors corresponding to the service routines for servicing the peripheral devices; priority encoder means responsive to said input means for producing priority signals to select interrupt address jump vectors from said read-only memory means in accordance with a predetermined priority basis in response to the interrupt request signals from the peripheral devices; control means responsive to said input means for transferring the contents of said program counter means into the microcomputer memory upon occurrence of an interrupt signal; multiplex means connected between the instruction bus of the microcomputer and said program counter means and operated by said control means in response to an interrupt request signal for coupling said read-only memory means to said program counter means to receive the corresponding interrupt address jump vectors therefrom; a second set of storage devices corresponding in number to the number of peripheral devices coupled to said enabling means and responsive to the interrupt request signals from different peripheral devices; and means for latching at any selected time said sets of storage devices to store the interrupt request signals therein while the corresponding interrupt address jump vectors are loaded in sequence into said program counter means to allow the peripheral devices requesting access to be serviced on the predetermined priority basis.

Claim 6

A priority interrupt system for a microcomputer having a program read only memory for storing service routines for servicing a plurality of peripheral devices, comprising: program counter means for stepping through the addresses of the program read-only memory in the microcomputer; input means for receiving interrupt request signals from the peripheral devices indicating requests for access to the microcomputer, said input means including a first set of storage devices corresponding in number to the number of peripheral devices and adapted to being coupled to a second set of storage devices for actuating a control means in response to an interrupt request signal; and enabling means coupling said first set of storage devices to a second set of storage devices to selectively enable and disable the transfer of the interrupt request signals from the first set of storage devices to said second set of storage devices: read-only memory means for storing interrupt address jump vectors corresponding to the service routines for servicing the peripheral devices; priority encoder means responsive to said input means for producing priority signals to select interrupt address jump vectors from said read-only memory means in accordance with a predetermined priority basis in response to the interrupt request signals from the peripheral devices; control means responsive to said input means for transferring the contents of said program counter means into the microcomputer memory upon occurrence of an interrupt signal; multiplex means connected between the instruction bus of the microcomputer and said program counter means and operated by said control means in response to an interrupt request signal for coupling said read-only memory means to said program counter means to receive the corresponding interrupt address jump vectors therefrom; a second set of storage devices corresponding in number to the number of peripheral devices coupled to said enabling means and responsive to the interrupt request signals from different peripheral devices; and means for latching at any selected time said sets of storage devices to store the interrupt request signals therein while the corresponding interrupt address jump vectors are loaded in sequence into said program counter means to allow the peripheral devices requesting access to be serviced on the predetermined priority basis.