Semiconductor memory test system

Claim 2

A semiconductor test system for testing a semiconductor memory wherein the semiconductor memory internalizes an arithmetic unit, comprising: a sequence control unit for generating sequence control signals; an address generator connected to an output of said sequence control unit for generating addresses having an output connected to the semiconductor memory under test; a data generator connected to the output of said sequence control unit for generating data; a data memory connected to an output of said address generator for storing irregular or random data; a clock generator connected to the output of said sequence control unit for supplying clock pulses to the semiconductor memory under test; a multiplexer connected to the output of said data generator and said data memory and having an output connected to the semiconductor memory for selecting which data to input to the semiconductor memory under test; a buffer memory having an address input connected to the output of said address generator and a data input connected to the output of said multiplexer, for storing identical data at identical addresses as the semiconductor memory under test; a control signal generator connected to the output of said sequence control unit and having an output connected to a write enable input terminal of said buffer memory for controlling the writing-in of data into said buffer memory; a logic comparator connected to an output of the semiconductor memory under test and an output of said buffer memory for comparing the data stored in the semiconductor memory and the buffer memory for determining whether the semiconductor memory under test functions correctly; and an arithmetic function unit having a first input connected to the output of said multiplexer, a second input connected to an output of said buffer memory, an output connected to the data input of said buffer memory, a third input connected to said control signal generator and a fourth input connected to said address generator, wherein a signal from said address generator sets a mode for an operation and a signal from said control signal generator starts the operation, results from the operation are stored in said buffer memory.

Claim 3

A semiconductor memory test system for testing a semiconductor memory wherein said semiconductor memory has a random access port and a serial access port and consists of a random access memory unit and a serial access memory unit, comprising: a sequence control unit for generating sequence control signals; an address generator connected to an output of said sequence control unit for generating addresses having an output connected to the semiconductor memory under test; a data generator connected to the output of said sequence control unit for generating data; a data memory connected to an output of said address generator for storing irregular or random data; a clock generator connected to the output of said sequence control unit for supplying clock pulses to the semiconductor memory under test; a multiplexer connected to the output of said data generator and said data memory and having an output connected to the semiconductor memory for selecting which data to input to the semiconductor memory under test; a buffer memory having an address input connected to the output of said address generator and a data input connected to the output of said multiplexer, for storing identical data at identical addresses as the semiconductor memory under test; a control signal generator connected to the output of said sequence control unit and having an output connected to a write enable input terminal of said buffer memory for controlling the writing-in of data into said buffer memory; a logic comparator connected to an output of the semiconductor memory under test and an output of said buffer memory for comparing the data stored in the semiconductor memory and the buffer memory for determining whether the semiconductor memory under test functions correctly; a counter connected to and controlled by said control signal generator having an input connected to said address signal generator for generating an address identical to an address used by the serial access memory unit of the semiconductor memory; and a second multiplexer connected to and controlled by said control signal generator having a first input connected to said address signal generator, a second input connected to said counter and an output connected to the address input of said buffer memory, for selecting between the address from said address signal generator and the address held in said counter for supply to said buffer memory.

Claim 4

A semiconductor memory test system for testing a semiconductor memory wherein said semiconductor memory has a random access port and a serial access port and consists of a random access memory unit and a serial access memory unit, comprising: a sequence control unit for generating sequence control signals; an address generator connected to an output of said sequence control unit for generating addresses having an output connected to the semiconductor memory under test; a data generator connected to the output of said sequence control unit for generating data; a data memory connected to an output of said address generator for storing irregular or random data; a clock generator connected to the output of said sequence control unit for supplying clock pulses to the semiconductor memory under test; a multiplexer connected to the output of said data generator and said data memory and having an output connected to the semiconductor memory for selecting which data to input to the semiconductor memory under test; a buffer memory having an address input connected to the output of said address generator and a data input connected to the output of said multiplexer, for storing identical data at identical addresses as the semiconductor memory under test; a control signal generator connected to the output of said sequence control unit and having an output connected to a write enable input terminal of said buffer memory for controlling the writing-in of data into said buffer memory; a logic comparator connected to an output of the semiconductor memory under test and an output of said buffer memory for comparing the data stored in the semiconductor memory and the buffer memory for determining whether the semiconductor memory under test functions correctly; a counter connected to and controlled by said control signal generator having an input connected to said address signal generator for generating an address identical to an address used by the serial access memory unit of the semiconductor memory; and a second multiplexer connected to and controlled by said control signal generator having a first input connected to said address signal generator, a second input connected to said counter and an output connected to the address input of said buffer memory, for selecting between the address from said address signal generator and the address held in said counter for supply to said buffer memory.

Claim 5

A semiconductor memory test system for testing a semiconductor memory according to claim 2, wherein the semiconductor memory has a random access memory and a serial access port and corresponding random access port and serial access memory which can be independently controlled, said system further comprising: a third multiplexer controlled by said control signal generator having a first input connected to said address generator and a second input connected to said counter, for selecting between the address supplied by said address generator and the address held in said counter; a second buffer memory for storing data identical to data stored in the serial access memory of the semiconductor memory, having a write enable terminal connected to the output of said control signal generator, a data input terminal connected to the output of said multiplexer and an address input terminal connected to the output of said third multiplexer, said buffer memory stores data identical to data stored in the random access memory of the semiconductor memory; and a fourth multiplexer controlled by said control signal generator for selecting between the data output by said buffer memory and the data output by said second buffer memory for supplying to said logic comparator.

Claim 6

A semiconductor test memory for testing a semiconductor memory wherein the semiconductor memory is a first-in first-out memory having a write-in pointer and a read out pointer, comprising: a sequence control unit for generating sequence control signals; an address generator connected to an output of said sequence control unit for generating addresses having an output connected to the semiconductor memory under test; a data generator connected to the output of said sequence control unit for generating data; a data memory connected to an output of said address generator for storing irregular or random data; a clock generator connected to the output of said sequence control unit for supplying clock pulses to the semiconductor memory under test; a multiplexer connected to the output of said data generator and said data memory and having an output connected to the semiconductor memory for selecting which data to input to the semiconductor memory under test; a buffer memory having an address input connected to the output of said address generator and a data input connected to the output of said multiplexer, for storing identical data at identical addresses as the semiconductor memory under test; a control signal generator connected to the output of said sequence control unit and having an output connected to a write enable input terminal of said buffer memory for controlling the writing-in of data into said buffer memory; a logic comparator connected to an output of the semiconductor memory under test and an output of said buffer memory for comparing the data stored in the semiconductor memory and the buffer memory for determining whether the semiconductor memory under test functions correctly; a first counter, controlled by said control signal generator and corresponding to the write-in pointer of the semiconductor memory, having an input connected to said address generator; a second counter, controlled by said control signal generator and corresponding to the read out pointer of the semiconductor memory, having an input connected to aid address generator; and a second multiplexer having a first input connected to said address generator, a second input connected to said first counter, and a third input connected to said second counter, controlled by said control signal generator, for selecting an address to supply to the address input of said buffer memory.

Claim 7

A semiconductor test memory for testing a semiconductor memory wherein the semiconductor memory is a first-in first-out memory having a write-in pointer and a read out pointer, comprising: a sequence control unit for generating sequence control signals; an address generator connected to an output of said sequence control unit for generating addresses having an output connected to the semiconductor memory under test; a data generator connected to the output of said sequence control unit for generating data; a data memory connected to an output of said address generator for storing irregular or random data; a clock generator connected to the output of said sequence control unit for supplying clock pulses to the semiconductor memory under test; a multiplexer connected to the output of said data generator and said data memory and having an output connected to the semiconductor memory for selecting which data to input to the semiconductor memory under test; a buffer memory having an address input connected to the output of said address generator and a data input connected to the output of said multiplexer, for storing identical data at identical addresses as the semiconductor memory under test; a control signal generator connected to the output of said sequence control unit and having an output connected to a write enable input terminal of said buffer memory for controlling the writing-in of data into said buffer memory; a logic comparator connected to an output of the semiconductor memory under test and an output of said buffer memory for comparing the data stored in the semiconductor memory and the buffer memory for determining whether the semiconductor memory under test functions correctly; a first counter, controlled by said control signal generator and corresponding to the write-in pointer of the semiconductor memory, having an input connected to said address generator; a second counter, controlled by said control signal generator and corresponding to the read out pointer of the semiconductor memory, having an input connected to aid address generator; and a second multiplexer having a first input connected to said address generator, a second input connected to said first counter, and a third input connected to said second counter, controlled by said control signal generator, for selecting an address to supply to the address input of said buffer memory.