Digital processing system including plural memory devices and data transfer circuitry

Claim 2

A digital processing system, comprising: first processor means for processing digital data in accordance with programmed instructions; second processor means for processing digital data in accordance with programmed instructions; a first random access memory (RAM) comprising a first plurality of memory cells for storing digital data; a second RAM comprising a second plurality of memory cells for storing digital data; input/output (I/O) means, responsive to external I/O signals, for providing access by said first processor means to the digital data stored in said first RAM and for providing access by said second processor means to the digital data stored in the second RAM; and control means, responsive to a plurality of transfer control signals, for copying selected segments of one of said first and second RAMs into segments of the other of said first and second RAMs, said control means including an enable register having a plurality of bit positions loaded by respective ones of said transfer control signals, with respective bit positions of said enable register corresponding to different ones of said segments and each bit having a first state to enable copying and a second, different state to inhibit copying of corresponding segments of said first and second RAMs.

Claim 3

A digital processing system, comprising: first processor means for processing digital data in accordance with programmed instructions; second processor means for processing digital data in accordance with programmed instructions; a first random access memory (RAM) comprising a first plurality of memory cells for storing digital data; a second RAM comprising a second plurality of memory cells for storing digital data; input/output (I/O) means, responsive to external I/O signals, for providing access by said first processor means to the digital data stored in said first RAM and for providing access by said second processor means to the digital data stored in the second RAM; and control means, responsive to a plurality of transfer control signals, for copying a selected portion of digital data stored in memory cells of one of said first and second RAMs into memory cells of the other of said first and second RAMs, said control means including an enable register having a plurality of bit positions loaded by respective ones of said transfer control signals, with respective bit positions of said enable register corresponding to different ones of said segments and each bit having a first state to enable copying and a second, different state to inhibit copying of corresponding segments of said first and second RAMs; a direction register having a plurality of bit positions loaded by respective ones of said transfer control signals, with respective bit positions of said direction register corresponding to different ones of said segments and each bit having a first state to direct copying from a corresponding segment of said first RAM to a corresponding segment in said second RAM and a second, different state to direct copying from that corresponding segment of said second RAM to that corresponding segment in said first RAM; wherein said I/O means further includes first read/write means for reading and writing data in said first RAM, and second read/write means, operating independently of said first read/write means, for reading and writing data in said second RAM.

Claim 4

A digital processing system, comprising: first processor means for processing digital data in accordance with programmed instructions; second processor means for processing digital data in accordance with programmed instructions; a first random access memory (RAM) comprising a first plurality of memory cells for storing digital data; a second RAM comprising a second plurality of memory cells for storing digital data; input/output (I/O) means, responsive to external I/O signals, for providing access by said first processor means to the digital data stored in said first RAM and for providing access by said second processor means to the digital data stored in the second RAM; and control means, responsive to a plurality of transfer control signals, for copying a selected portion of digital data stored in memory cells of one of said first and second RAMs into memory cells of the other of said first and second RAMs, said control means including an enable register having a plurality of bit positions loaded by respective ones of said transfer control signals, with respective bit positions of said enable register corresponding to different ones of said segments and each bit having a first state to enable copying and a second, different state to inhibit copying of corresponding segments of said first and second RAMs; a direction register having a plurality of bit positions loaded by respective ones of said transfer control signals, with respective bit positions of said direction register corresponding to different ones of said segments and each bit having a first state to direct copying from a corresponding segment of said first RAM to a corresponding segment in said second RAM and a second, different state to direct copying from that corresponding segment of said second RAM to that corresponding segment in said first RAM; wherein said I/O means further includes first read/write means for reading and writing data in said first RAM, and second read/write means, operating independently of said first read/write means, for reading and writing data in said second RAM.

Claim 5

The digital processing system of claim 2 wherein said first read/write means includes a first buffer and a first sense amplifier operatively coupled between said first RAM and an I/O multiplexer, said first buffer being coupled to a first write input terminal and said first sense amplifier being coupled to a first read output terminal; and wherein said second read/write means includes a second buffer and a second sense amplifier operatively coupled between said second RAM and said I/O multiplexer, said second buffer being coupled to a second write input terminal and said second sense amplifier being coupled to a second read output terminal.