US4942575A
Expired / Lapsed
US
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Error connection device for parity protected memory systems
Assignee: Modular Computer Systems Inc
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Filing: 1988-06-17
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Granted: 1990-07-17
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Expires: 2008-06-17
Abstract
Abstract The use of a redundant memory subsystem, memory flow control, and a method of copying (srubbing) data from the location of one memory subsystem to the corresponding location in the other memory subsystem provides correction of soft errors in a parity protected memory system without degrading the performance of the memory system except when an error occurs. A copy of the correct data is also provided to the memory system when a location in either of the memory subsystems experiences a hard error.
Inventors
- 👤 William E. Earnshaw
- 👤 Jay Howell
- 👤 Paul B. Ripy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:14
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/74; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G06F11/106
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
75 words
A memory system with error detection and correction circuitry for returning error free data to a main system bus, comprising: two memory subsystems each for performing read and write operations; and error detection and correction means coupled between said two memory subsystems for allowing only one of said memory subsystems to return error free data to the main bus system as long as at least one of said two memory subsystems contains error free data.
Claim 2
Dependent Claim
75 words
A memory system with error detection and correction circuitry for returning error free data to a main system bus, comprising: two memory subsystems each for performing read and write operations; and error detection and correction means coupled between said two memory subsystems for allowing only one of said memory subsystems to return error free data to the main bus system as long as at least one of said two memory subsystems contains error free data.
Claim 3
Dependent Claim
40 words
A memory system as defined in claim 1, wherein said error detection and correction means includes communication means for communicating between said two memory subsystems to determine which subsystem is to return error free data to the main system bus.
Claim 4
Dependent Claim
38 words
A memory system as defined in claim 1, wherein said error detection and correction means permits no data to be returned to said main bus system when both memory subsystems experience an error during a given read operation.
Claim 5
Dependent Claim
58 words
A memory system as defined in claim 1, wherein said error detection and correction means includes flow control means for causing error free data returned to the main system bus from one memory subsystem to be written into a corresponding memory location of the other memory subsystem if said other memory subsystem is determined to contain erroneous data.
Claim 6
Dependent Claim
18 words
A memory system as defined in claim 1, wherein said two memory subsystems operate synchronously to each other.
Claim 7
Dependent Claim
24 words
A memory system as defined in claim 1, wherein said communication means communicates between said two memory subsystems without affecting the main system bus.
Claim 8
Dependent Claim
194 words
A memory system as defined in claim 1, wherein said error detection and correction means includes for each memory subsystem: parity check logic means connected to the memory subsystem and having an output for producing a logic true signal representing that no error has occurred in the memory subsystem and a logic false signal representing that an error has occured in the memory subsystem; a NOR-gate having first and second inputs and an output; and an AND-gate having first and second inputs, the first input of said AND-gate being connected to the output of said parity check logic means and the second input of said AND-gate being connected to the output of said NOR-gate, the first input of said NOR-gate being connected for receiving a logical true signal if the memory subsystem is allowed to put data on the system main bus and receiving a logical false signal if the memory subsystem is not allowed to put data on the system main bus, and the second input of said NOR-gate being connected for receiving the parity check logic signal from the parity check logic means associated with the other one of the memory subsystems.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-16 | 1994-01-15 | 1994-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-16 | 1998-01-15 | 1998-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-16 | 2002-01-15 | 2002-07-17 | $7700.00 | Window Closed / Lapsed |