US4752914A — Semiconductor integrated circuit with redundant c…

Claim 1

Independent Claim 178 words

A semiconductor integrated circuit having a plurality of external connection terminals and operable in response to input address data including a plurality of input address bits applied via at least some of the external connection terminals, said semiconductor integrated circuit comprising: memory means for storing address information comprising a plurality of address bits corresponding to a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion; comparison means for detecting coincidence between the plurality of address bits forming the address information and the input address bits forming the input address data, and for generating comparison data at plural output nodes; and output circuit means, connected to the output nodes of said comparison means and to one of the external connection terminals, for delivering a coincidence output through said one of the external connection terminals when the comparison data indicates complete coincidence between all the input address bits and all the stored addess bits, respectively, so that the write state of said memory means can be detected based on the received input address data.

Claim 2

Dependent Claim 178 words

A semiconductor integrated circuit having a plurality of external connection terminals and operable in response to input address data including a plurality of input address bits applied via at least some of the external connection terminals, said semiconductor integrated circuit comprising: memory means for storing address information comprising a plurality of address bits corresponding to a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion; comparison means for detecting coincidence between the plurality of address bits forming the address information and the input address bits forming the input address data, and for generating comparison data at plural output nodes; and output circuit means, connected to the output nodes of said comparison means and to one of the external connection terminals, for delivering a coincidence output through said one of the external connection terminals when the comparison data indicates complete coincidence between all the input address bits and all the stored addess bits, respectively, so that the write state of said memory means can be detected based on the received input address data.

Claim 3

Dependent Claim 20 words

A circuit according to claim 1, wherein said memory means comprises a fuse and a transistor connected to said fuse.

Claim 4

Dependent Claim 74 words

A circuit according to claim 1, wherein said memory means comprises a plurality of memory cells, further comprising: a terminal commonly connected to said plural memory cells; and status detection means for delivering a status signal indicating the written state of one of said plurality of memory cells in said memory means from said terminal commonly connected to said plural memory cells, by supplying a specific address signal corresponding to said one memory cell.

Claim 5

Dependent Claim 22 words

A circuit according to claim 3, wherein each of said memory cells comprises a fuse and a transistor connected to said fuse.

Claim 6

Dependent Claim 33 words

A circuit according to claim 3, further comprising a detection line and a voltage source, wherein said status detection means comprises transistors connected in series between said detection line and said voltage source.

Claim 7

Dependent Claim 45 words

A circuit according to claim 3, further comprising a detection line and a voltage source, wherein said status detection means comprises a series connection of a transistor and parallel connected sets of series connections of transistors, connected between said detection line and said voltage source.

Claim 8

Dependent Claim 58 words

A circuit according to claim 3, further comprising first and second detection lines and a voltage source, wherein said status detection means comprises: a first set of transistors connected in series between said first detection line and said voltage source; and a second set of transistors connected in series between said second detection line and said voltage source.

Claim 9

Dependent Claim 49 words

A circuit according to claim 3, further comprising a detection line and a voltage source, wherein said status detection means comprises a series connection of a set of series connected transistors and parallel connected sets of series connections of transistors, connected between said detection line and said voltage source.

Claim 10

Dependent Claim 136 words

A semiconductor integrated circuit operatively connected to receive an input address formed by input address bits and having a redundant circuit portion for replacing a failed circuit portion, comprising: a memory for storing address information, formed by stored address bits, corresponding to the failed circuit portion and for providing the address information for accessing the redundant circuit portion in place of the failed circuit portion; comparison means, operatively connected to said memory and operatively connected to receive the input address, for detecting coincidence between the stored address bits read from said memory and the input address bits and for generating comparison data; and output circuit means, connected to said comparison means, for providing the comparison data from said comparison means, said output circuit means including an external connection terminal through which the comparison data is provided.

Claim 11

Dependent Claim 136 words

A semiconductor integrated circuit operatively connected to receive an input address formed by input address bits and having a redundant circuit portion for replacing a failed circuit portion, comprising: a memory for storing address information, formed by stored address bits, corresponding to the failed circuit portion and for providing the address information for accessing the redundant circuit portion in place of the failed circuit portion; comparison means, operatively connected to said memory and operatively connected to receive the input address, for detecting coincidence between the stored address bits read from said memory and the input address bits and for generating comparison data; and output circuit means, connected to said comparison means, for providing the comparison data from said comparison means, said output circuit means including an external connection terminal through which the comparison data is provided.

Claim 12

Dependent Claim 66 words

A circuit according to claim 9, wherein said memory comprises a plurality of memory cells, said circuit further comprising: a terminal commonly connected to said plural memory cells; and status detection means, operatively connected to said terminal, for providing a status signal, indicating the state of one of said memory cells, from said terminal by supplying a specific address signal corresponding to said one memory cell.

Claim 13

Dependent Claim 22 words

A circuit according to claim 10, wherein each of said memory cells comprises a fuse and a transistor connected to said fuse.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1991-06-21	1991-12-21	1992-06-21	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1995-06-21	1995-12-21	1996-06-21	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1999-06-21	1999-12-21	2000-06-21	$7700.00	Window Closed / Lapsed

Semiconductor integrated circuit with redundant circuit replacement

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