A Ram cell having means for controlling a bidirectional shift

Claim 2

A memory cell comprising: a cross-coupled master latch formed of a first inverter and a second inverter, said first inverter having its output connected to the input of said second inverter and to a true data output node, said second inverter having its output connected to the input of said first inverter and to a complementary data output node; a cross-coupled slave latch formed of a third inverter and a fourth inverter, said third inverter having its output connected to the input of said fourth inverter and to a true data output node, said fourth inverter having its output connected to the input of said third inverter and to a complementary data output node; means operatively connected to said master latch and said slave latch for controlling bidirectional shifting of data between the true and complementary data nodes of said slave latch; first shift enable means interconnected between said master latch and said slave latch; and second shift enable means connected between said master latch and a slave latch in an adjoining memory cell.

Claim 3

A memory cell as claimed in claim 1, wherein said control means includes means for switching off and on a power supply connected to said master latch.

Claim 4

A memory cell as claimed in claim 2, wherein data is shifted to said master latch when said power supply connected to said master latch is switched off.

Claim 5

A memory cell as claimed in claim 1, wherein said first inverter comprises a P-channel MOS transistor and an N-channel MOS transistor, said P-channel and N-channel transistors having their gates connected together to define the input thereof and their drains connected together to define the output thereof, said P-channel transistor having its source connected to a supply potential, said N-channel transistor having its source connected to a ground potential.

Claim 6

A memory cell as claimed in claim 4, wherein said second inverter comprises a P-channel MOS transistor and an N-channel MOS transistor, said P-channel and N-channel transistors having their gates connected together to define the input thereof and their drains connected together to define the output thereof, said P-channel transistor having its source connected to a supply potential, said N-channel transistor having its source connected to a ground potential.

Claim 7

A memory cell as claimed in claim 5, wherein said third inverter comprises a P-channel MOS transistor and an N-channel MOS transistor, said P-channel and N-channel transistors having their gates connected together to define the input thereof and their drains connected together to define the output thereof, said P-channel transistor having its source connected to a supply potential, said N-channel transistor having its source connected to a ground potential.

Claim 8

A memory cell as claimed in claim 6, wherein said fourth inverter comprises a P-channel MOS transistor and an N-channel MOS transistor, said P-channel and N-channel transistors having their gates connected together and to define the input thereof and their drains connected together to define the output thereof, said P-channel transistor having its source connected to a supply potential, said N-channel transistor having its source connected to a ground potential.

Claim 9

A memory cell as claimed in claim 1, wherein first shift enable means comprises first and second shift enable transistors having their main terminals connected between the true/complementary data output nodes of said master latch and the true/complementary data output node of said slave latch, and wherein said second shift enable means comprises third and fourth shift enable transistors having their main electrodes connected between the true/complementary data output nodes of said master latch and the true/complementary data output nodes of the slave latch in the adjoining memory cell.

Claim 10

A memory cell as claimed in claim 8, further comprising a first row select transistor connected to said true data output node of said master latch and a second row select transistor connected to the complementary data output node of said master latch.

Claim 11

A memory device comprising: a plurality of memory cells which are arranged in a column, each of said memory cell being formed of a master cell and a slave cell; each master cell having a pair of data nodes; each master cell including a cross-coupled master latch formed of a first inverter and a second inverter, said first inverter having its output connected to the input of said second inverter and to one of said pair of data nodes, said second inverter having its output connected to the input of said first inverter and to the other one of said pair of data nodes; each slave cell having a pair of data nodes; each slave cell including a cross-coupled slave latch formed of a third inverter and a fourth inverter, said third inverter having its output connected to the input of said fourth inverter and to one of said pair of data nodes; said fourth inverter having its output connected to the input of said third inverter and to the other one of said pair of data nodes; a first pair of shift enable transistors connected between the paired data nodes in each master cell and the paired data nodes in each slave cell; a second pair of shift enable transistors connected between the paired data nodes in each master cell and the paired data nodes in an adjacent slave cell of a memory cell having a lower address; a pair of bit sense lines common to said plurality of memory cells arranged in the column; transfer gate means connected between the paired data nodes in each master cell and the paired common bit sense lines for reading and writing randomly data from/to each master cell; and means for switching on and off a power supply connected to each master cell for controlling a directional shifting of data, data being received in each master cell from one of the adjoining slave cells when the power supply is switched off in the master cell.

Claim 12

A memory device comprising: a plurality of memory cells which are arranged in a column, each of said memory cell being formed of a master cell and a slave cell; each master cell having a pair of data nodes; each master cell including a cross-coupled master latch formed of a first inverter and a second inverter, said first inverter having its output connected to the input of said second inverter and to one of said pair of data nodes, said second inverter having its output connected to the input of said first inverter and to the other one of said pair of data nodes; each slave cell having a pair of data nodes; each slave cell including a cross-coupled slave latch formed of a third inverter and a fourth inverter, said third inverter having its output connected to the input of said fourth inverter and to one of said pair of data nodes; said fourth inverter having its output connected to the input of said third inverter and to the other one of said pair of data nodes; a first pair of shift enable transistors connected between the paired data nodes in each master cell and the paired data nodes in each slave cell; a second pair of shift enable transistors connected between the paired data nodes in each master cell and the paired data nodes in an adjacent slave cell of a memory cell having a lower address; a pair of bit sense lines common to said plurality of memory cells arranged in the column; transfer gate means connected between the paired data nodes in each master cell and the paired common bit sense lines for reading and writing randomly data from/to each master cell; and means for switching on and off a power supply connected to each master cell for controlling a directional shifting of data, data being received in each master cell from one of the adjoining slave cells when the power supply is switched off in the master cell.

Claim 13

A memory device as claimed in claim 10, wherein said master cell comprises a static random access memory cell.

Claim 14

A memory device as claimed in claim 11, wherein said slave cell comprises a static random access memory cell.