US4633440A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-port memory chip in a hierarchical memory
Assignee: International Business Machines Corp
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Filing: 1984-12-31
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Granted: 1986-12-30
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Expires: 2004-12-31
Abstract
Abstract A hierarchical memory system in which a lower level transfers data serially to an upper level and in parallel to a yet lower level. The lower level includes a two-port memory chip having a wide buffer for parallel accesses to the memory array, to the yet lower level, and to a serial buffer. The serial buffer is serially accessed to the upper level simultaneously with accesses to the wide buffer.
Inventors
- 👤 Francis J. Pakulski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:51
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0884
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
160 words
A hierarchical memory system having at least two levels comprising a first and second memory chip, the first memory chip being the higher level memory and the second chip being the lower level memory, said second chip comprising: a memory array with a primary buffer; master and slave registers as a secondary buffer, connected to the primary buffer, said slave register being bidirectionally coupled for data transfer to the master register and to said first memory chip; said system further comprising: means for serially transferring an entire row of memory information between the first chip and the slave register on said second chip in a selected direction; means for simultaneously transferring in a random access an entire row of memory information between said memory array and said primary buffer in a selected direction; means for transferring information between the master register and the slave register; and means for accessing of said master and slave registers from outside said second chip.
Claim 2
Dependent Claim
160 words
A hierarchical memory system having at least two levels comprising a first and second memory chip, the first memory chip being the higher level memory and the second chip being the lower level memory, said second chip comprising: a memory array with a primary buffer; master and slave registers as a secondary buffer, connected to the primary buffer, said slave register being bidirectionally coupled for data transfer to the master register and to said first memory chip; said system further comprising: means for serially transferring an entire row of memory information between the first chip and the slave register on said second chip in a selected direction; means for simultaneously transferring in a random access an entire row of memory information between said memory array and said primary buffer in a selected direction; means for transferring information between the master register and the slave register; and means for accessing of said master and slave registers from outside said second chip.
Claim 3
Dependent Claim
38 words
A hierarchical memory system as recited in claim 1, wherein said row is subdivided into sub-rows and said accessing means includes means for randomly accessing each sub-row of information of the row of information in said primary buffer.
Claim 4
Dependent Claim
28 words
A hierarchical memory system as recited in claim 1, wherein said means for transferring information between said primary and secondary buffers simultaneously transfers an entire row of information.
References Cited (Backward Citations)
US4402067A
Cited
US4489381A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-29 | 1990-06-30 | 1990-12-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-29 | 1994-06-30 | 1994-12-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-29 | 1998-06-30 | 1998-12-30 | $7700.00 | Window Closed / Lapsed |