US4402067A
Expired / Lapsed
US
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Bidirectional dual port serially controlled programmable read-only memory
Assignee: Individual
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Filing: 1978-02-21
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Granted: 1983-08-30
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Expires: 1998-02-21
Abstract
Abstract A bidirectional serially controlled programmable read-only memory has a serial input/output (I/O) port and a parallel I/O port. By selecting the appropriate control inputs, the instant invention can receive serial address or data information and output data to either the parallel or serial I/O ports. In a like manner, an address at the parallel I/O port can be utilized to generate output data in either a serial or parallel form. In general, the parallel I/O port will be utilized to transfer data to and from a microprocessor, whereas the serial I/O port will be utilized to transfer data to and from an external interface. By proper utilization of the control circuits and appropriate use of the control signals, data may be read from the bidirectional PROM in parallel form from the parallel I/O port or in serial form from the serial I/O port. In addition, data may be transferred from the serial I/O port to the parallel I/O port or from the parallel I/O port to the serial I/O port. Multiplexing means and register means interact with the control circuits to formulate the data transfers.
Inventors
- 👤 William E. Moss
- 👤 Shlomo Waser
- 👤 Ury Priel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:28
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/16; G11C17/00; G11C17/08; G11C17/10; G11C17/12
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
219 words
A bidirectional dual port serially controlled electronically programmable read-only memory comprising, in combination: means for receiving a plurality of control input signals; serial input/output port means for transmitting data to and receiving data from said read-only memory in serial form; plural bit address bus means providing parallel addressing information; plural bit bidirectional parallel data bus means for transmitting and receiving data in parallel form; register means for temporary storage of address and data information, said register means coupled to said serial input/output port means for providing serial output data and coupled to said data bus means for providing parallel output data; multiplexing means coupled to said register means, said address bus means, said data bus means and said serial input/output port means for selectively switching data; control means responsive to said control input signals and coupled to said register means, said address bus means, said serial input/output port means and said multiplexing means for controlling the interaction of said register means, said multiplexing means, said address bus means, said data bus means, and said serial input/output port means; nonvolatile memory means coupled to said multiplexing means for producing a plural bit data output; and means for permanently storing in a portion of said nonvolatile memory means data contained in said register means, said portion determined by said multiplexing means.
Claim 2
Dependent Claim
219 words
A bidirectional dual port serially controlled electronically programmable read-only memory comprising, in combination: means for receiving a plurality of control input signals; serial input/output port means for transmitting data to and receiving data from said read-only memory in serial form; plural bit address bus means providing parallel addressing information; plural bit bidirectional parallel data bus means for transmitting and receiving data in parallel form; register means for temporary storage of address and data information, said register means coupled to said serial input/output port means for providing serial output data and coupled to said data bus means for providing parallel output data; multiplexing means coupled to said register means, said address bus means, said data bus means and said serial input/output port means for selectively switching data; control means responsive to said control input signals and coupled to said register means, said address bus means, said serial input/output port means and said multiplexing means for controlling the interaction of said register means, said multiplexing means, said address bus means, said data bus means, and said serial input/output port means; nonvolatile memory means coupled to said multiplexing means for producing a plural bit data output; and means for permanently storing in a portion of said nonvolatile memory means data contained in said register means, said portion determined by said multiplexing means.
Claim 3
Dependent Claim
45 words
The bidirectional dual port serially controlled electronically programmable read-only memory as recited in claim 1 wherein said multiplexing means further comprises: a plurality of multiplexers each of which is controlled by said control means for selecting one of a plurality of plural bit data/address words.
Claim 4
Dependent Claim
153 words
The bidirectional dual port serially controlled electronically programmable read-only memory as recited in claim 1 wherein said control means comprises: a serial shift register loadable from said serial input/output port means for providing a first plurality of control signals, said serial shift register responsive to a first plurality of said control input signals; a first decoding means coupled to said address bus means for providing a second plurality of control signals dependant upon the state of said address bus means: second decoding means responsive to a second plurality of said control input signals for providing a third plurality of control signals dependant upon the state of said second plurality of said control input signals; and first status means responsive to said first and second decoding means for providing a first status signal to allow said serial input/output port means to control operation of the bidirectional dual port serially controlled electronically programmed read-only memory.
Claim 5
Dependent Claim
41 words
The bidirectional dual port serially controlled electronically programmed read-only memory as recited in claim 1 wherein said nonvolatile memory means further comprises: a plural bit, multiple word, electronically programmable read-only memory; and selection means connected to said electronically programmable read-only memory.
Claim 6
Dependent Claim
141 words
A memory system comprising, in combination, data bus means for carrying information; memory means coupled to said data bus means for storing said information; input/output means for providing addressing and control information to said memory means and data information to said data bus means; and control means coupled to said data bus means, said input/output means and said memory means, for transferring parallel data information to and from said data bus means and serial data information to and from said input/output means, said control means comprising: multiplexing means for selectively switching data and address information to said data bus means, memory means and input/output means; and register means coupled to said multiplexing means for transforming information from a serial format to a parallel format and from a parallel format to a serial format, said register means also storing said control information.
Claim 7
Dependent Claim
141 words
A memory system comprising, in combination, data bus means for carrying information; memory means coupled to said data bus means for storing said information; input/output means for providing addressing and control information to said memory means and data information to said data bus means; and control means coupled to said data bus means, said input/output means and said memory means, for transferring parallel data information to and from said data bus means and serial data information to and from said input/output means, said control means comprising: multiplexing means for selectively switching data and address information to said data bus means, memory means and input/output means; and register means coupled to said multiplexing means for transforming information from a serial format to a parallel format and from a parallel format to a serial format, said register means also storing said control information.
Claim 8
Dependent Claim
21 words
A memory system as recited in claim 5 wherein said data bus means further comprises a plural bit bidirectional communication means.
Claim 9
Dependent Claim
17 words
A memory system as recited in claim 5 wherein said memory means comprises a programmable read-only memory.
Claim 10
Dependent Claim
28 words
A memory system as recited in claim 7 wherein said programmable read-only memory means comprises an electronically programmable read-only memory of the type wherein fuse-links are selectively destroyed.
Claim 11
Dependent Claim
113 words
A programmable read only memory (PROM) of a type having a non-volatile memory with fusible links that are selectively blown to cause said PROM to provide predetermined logic signals in response to an address that is applied in parallel at parallel ports and serially at a serial port, comprising: register means for storing said serial address; multiplexer means for alternatively providing said stored serial address and said parallel address to said nonvolatile memory in response to a control signal; and control means for transmitting a data word from said non-volatile memory serially to said serial port and in parallel through a data bus to said parallel ports in response to a control signal.
Claim 12
Dependent Claim
113 words
A programmable read only memory (PROM) of a type having a non-volatile memory with fusible links that are selectively blown to cause said PROM to provide predetermined logic signals in response to an address that is applied in parallel at parallel ports and serially at a serial port, comprising: register means for storing said serial address; multiplexer means for alternatively providing said stored serial address and said parallel address to said nonvolatile memory in response to a control signal; and control means for transmitting a data word from said non-volatile memory serially to said serial port and in parallel through a data bus to said parallel ports in response to a control signal.
Claim 13
Dependent Claim
21 words
A programmable read-only memory system in accordance with claim 9 including means for coupling input information serially into said register means.
Claim 14
Dependent Claim
21 words
A programmable read-only memory system in accordance with claim 1 including means for coupling information serially out of said register means.
Claim 15
Dependent Claim
40 words
A programmable read-only memory system in accordance with claim 10 wherein said register means having means for storing information that is read out of said programmable read-only memory array, including means for coupling information serially out of said register means.
Claim 16
Dependent Claim
22 words
A programmable read-only memory system in accordance with claim 9 including means for coupling input information in parallel into said register means.
Claim 17
Dependent Claim
22 words
A programmable read-only memory system in accordance with claim 9 including means for coupling information in parallel out of said register means.
Claim 18
Dependent Claim
22 words
A programmable read-only memory system in accordance with claim 13 including means for coupling information in parallel out of said register means.
Claim 19
Dependent Claim
25 words
A programmable read-only memory system in accordance with claim 9 including means for coupling information selectively in serial or in parallel into said register means.
Claim 20
Dependent Claim
26 words
A programmable read-only memory system in accordance with claim 1 including means for coupling information selectively in serial or in parallel out of said register means.
Claim 21
Dependent Claim
45 words
A programmable read-only memory system in accordance with claim 16 wherein said register means having means for storing information that is read out of said programmable read-only memory array, including means for coupling information selectively in serial or in parallel out of said register means.
Claim 22
Dependent Claim
29 words
A programmable read-only memory system in accordance with claim 9 including selection means coupled to said register means for initiating a programming operation in said programmable read-only memory array.
Claim 23
Dependent Claim
33 words
A programmable read-only memory system in accordance with claim 19 wherein said selection means comprising means for enabling said register means to select locations in said programmable read-only memory array to be programmed.
Claim 24
Dependent Claim
29 words
A programmable read-only memory system in accordance with claim 19 wherein said selection means includes means for selecting for programming only a single bit in said read-only memory array.
Claim 25
Dependent Claim
29 words
A programmable read-only memory system in accordance with claim 9 wherein said register means having means for storing information that is read out of said programmable read-only memory array.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-29 | 1987-02-28 | 1987-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-29 | 1991-02-28 | 1991-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-29 | 1995-02-28 | 1995-08-30 | $7700.00 | Window Closed / Lapsed |