US4128900A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable read only memory for electronic engine control
Assignee: Old Carco LLC
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Filing: 1978-02-06
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Granted: 1978-12-05
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Expires: 1998-02-06
Abstract
Abstract An electronic engine control system comprises a central microprocessor integrated circuit, a program memory integrated circuit, and a programmable read only memory integrated circuit. The central microprocessor integrated circuit carries out calculations used in controlling an event associated with the engine according to a basic program contained in the program memory integrated circuit. The programmable read only memory integrated circuit is programmed to tailor the basic program contained in the program memory integrated circuit for the particular engine with which the electronic control system is utilized.
Inventors
- 👤 John P. Lappington
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:41
CPC Classifications
F; F02; F02D; F02D41/00; F02D41/24; F02D41/2406; F02D41/2425; F02P; F02P15/00; F02P15/001
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
121 words
A programmable read only memory integrated circuit and associated circuitry for reading and writing data from and on the programmable read only memory integrated circuit comprising in combination: an address bus containing an address latch circuit; means connecting the address bus to the address input of the programmable read only memory integrated circuit; a bi-directional data bus containing a tri-state latch circuit and an output buffer drive circuit connected in parallel; means connecting said bi-directional data bus to the data input/output of the programmable read only memory integrated circuit; and control means for reading and writing data from and on the programmable read only memory integrated circuit via said bi-direcitonal data bus in accordance with addresses supplied via said address bus.
Claim 2
Dependent Claim
121 words
A programmable read only memory integrated circuit and associated circuitry for reading and writing data from and on the programmable read only memory integrated circuit comprising in combination: an address bus containing an address latch circuit; means connecting the address bus to the address input of the programmable read only memory integrated circuit; a bi-directional data bus containing a tri-state latch circuit and an output buffer drive circuit connected in parallel; means connecting said bi-directional data bus to the data input/output of the programmable read only memory integrated circuit; and control means for reading and writing data from and on the programmable read only memory integrated circuit via said bi-direcitonal data bus in accordance with addresses supplied via said address bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-12-04 | 1982-06-05 | 1982-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-12-04 | 1986-06-05 | 1986-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-12-04 | 1990-06-05 | 1990-12-05 | $7700.00 | Window Closed / Lapsed |