Non-volatile ram cell with charge pumps

Claim 2

A memory cell circuit comprising: a flip-flop having first and second stable states; means for establishing said flip-flop in said first state; a non-volatile storage element having first and second states corresponding to said first and second states of said flip-flop, respectively, said non-volatile element including a terminal having a predetermined voltage when said non-volatile element is in said second state; and a transfer circuit connected to said flip-flop and to said non-volatile element, for selectively connecting said flip-flop to said terminal after said flip-flop has been established in said first state, so that when said terminal has said predetermined voltage said flip-flop is flipped to said second state, but that when said terminal does not have said predetermined voltage said flip-flop remains in said first state.

Claim 3

The memory cell circuit of claim 1 wherein said transfer circuit selectively transfers the state of said flip-flop to said non-volatile element.

Claim 4

The memory cell circuit of claim 2 wherein said non-volatile element comprises: a charge storage device for storing a charge representative of the state of said non-volatile element; and a sensing element for connecting a source of said predetermined voltage to said terminal when said charge storage device stores a charge representative of said second state.

Claim 5

The memory cell circuit of claim 3 wherein : said charge storage device comprises a first floating gate MOSFET having a control gate, a floating gate, and a diffusion; and said sensing element comprises a second floating gate MOSFET having a control gate, a floating gate, and a channel, and having its floating gate connected to the floating gate of said first floating gate MOSFET and having its channel connected between said terminal and said voltage source.

Claim 6

The memory cell circuit of claim 4 additionally comprising: a first charge pump connected to the control gate of said charge storage device; and a second charge pump connected to the diffusion of said charge storage device; wherein, to place said non-volatile element in said first state, said first charge pump is turned on to apply a voltage to said control gate of said charge storage device and place a first charge on said floating gate; and wherein, to place said non-volatile element in said second state, said second charge pump is turned on to apply a voltage to said diffusion of said charge storage device and place a second charge on said floating gate.

Claim 7

The memory cell circuit of claim 5 wherein: said first charge pump is connected so that when said transfer circuit transfers said first state of said flip-flop to said non-volatile element, said first charge pump is turned on; and said second charge pump is connected so that when said transfer circuit transfers said second state of said flip-flop to said non-volatile element, said second charge pump is turned on.

Claim 8

A memory cell circuit comprising: a volatile cell including first and second nodes having first and second stable states; a non-volatile cell including: third and fourth nodes selectively connectable to said first and second nodes; a charge storage device connected to said third and fourth nodes for storing a first or second charge representative of the state of said third and fourth nodes; and a sensing device selectively connectable to said volatile cell and responsive to said charge storage device to cause a predetermined voltage to be supplied to one of said volatile cell nodes, but not to the other to cause said volatile element nodes to assume a predetermined one of their states depending on the charge stored on said charge storage device; wherein said sensing device includes: an output terminal that is coupled to a predetermined voltage source when said charge storage device is storing said second charge, and a transfer control circuit for selectively coupling one of said volatile element nodes to said output terminal.

Claim 9

A memory cell circuit comprising: a volatile cell including first and second nodes having first and second stable states; a non-volatile cell including: third and fourth nodes selectively connectable to said first and second nodes; a charge storage device connected to said third and fourth nodes for storing a first or second charge representative of the state of said third and fourth nodes; and a sensing device selectively connectable to said volatile cell and responsive to said charge storage device to cause a predetermined voltage to be supplied to one of said volatile cell nodes, but not to the other to cause said volatile element nodes to assume a predetermined one of their states depending on the charge stored on said charge storage device; wherein said sensing device includes: an output terminal that is coupled to a predetermined voltage source when said charge storage device is storing said second charge, and a transfer control circuit for selectively coupling one of said volatile element nodes to said output terminal.

Claim 10

The memory cell circuit defined in claim 7 wherein: said third and fourth nodes have first and second states corresponding to the first and second states of said first and second nodes, respectively; said charge storage device stores first and second charges representative of the first and second states of said third and fourth nodes, respectively; said terminal has said predetermined voltage when said charge storage device has said second charge; and said transfer circuit selectively connects said predetermined volatile cell node to said terminal to cause said node to attain substantially the same voltage as said terminal when said charge storage device has said second charge to cause said volatile cell to assume said second state.

Claim 11

The memory cell circuit of claim 7, additionally comprising means for establishing said volatile cell in said first state before said transfer control circuit couples said volatile element node to said output terminal.

Claim 12

A memory cell circuit comprising: a volatile cell including first and second nodes having first and second stable states: a non-volatile cell including: third and fourth nodes having first and second states corresponding to the first and second states of said first and second nodes, respectively; a charge storage device for storing first and second charges representative of the first and second states of said third and fourth nodes, respectively; and a terminal having a predetermined voltage when said charge storage device is storing said second charge; and a transfer circuit for selectively transferring the state of said first and second nodes to said third and fourth nodes, and for selectively connecting a predetermined one of said volatile cell nodes to said terminal so that when said charge storage device has said second charge and said terminal is at said predetermined voltage, said connected volatile cell node attains substantially the same voltage as said terminal to cause said volatile cell to assume said second state; and wherein: said charge storage device comprises a first floating gate field effect transistor wherein said first and second charges are stored on the floating gate thereof; and said non-volatile cell further comprises a sensing device comprising a second floating gate field effect transistor having a control gate, a floating gate, and a channel, and having its floating gate connected to the floating gate of said first floating gate field effect transistor, and having its channel connected between said terminal and a source of said predetermined voltage.

Claim 13

A memory cell circuit comprising: a volatile cell including first and second nodes having first and second stable states: a non-volatile cell including: third and fourth nodes having first and second states corresponding to the first and second states of said first and second nodes, respectively; a charge storage device for storing first and second charges representative of the first and second states of said third and fourth nodes, respectively; and a terminal having a predetermined voltage when said charge storage device is storing said second charge; and a transfer circuit for selectively transferring the state of said first and second nodes to said third and fourth nodes, and for selectively connecting a predetermined one of said volatile cell nodes to said terminal so that when said charge storage device has said second charge and said terminal is at said predetermined voltage, said connected volatile cell node attains substantially the same voltage as said terminal to cause said volatile cell to assume said second state; and wherein: said charge storage device comprises a first floating gate field effect transistor wherein said first and second charges are stored on the floating gate thereof; and said non-volatile cell further comprises a sensing device comprising a second floating gate field effect transistor having a control gate, a floating gate, and a channel, and having its floating gate connected to the floating gate of said first floating gate field effect transistor, and having its channel connected between said terminal and a source of said predetermined voltage.

Claim 14

A memory cell circuit comprising: a volatile cell including first and second nodes having first and second stable states; a non-volatile cell including third and fourth nodes, a charge storage device for storing a charge representative of the state of said third and fourth nodes, and a terminal having a predetermined voltage when said charge storage device stores a charge representative of a predetermined one of the states of said third and fourth nodes; a transfer circuit for selectively transferring the state of said first and second nodes to said third and fourth nodes, and for selectively connecting a predetermined one of said volatile cell nodes to said terminal so that if said terminal is at said predetermined voltage said connected volatile cell node attains essentially the same voltage as said terminal; a first charge pump connected to said third node so that when a voltage is transferred from said first node to said third node, said first charge pump is turned on; and a second charge pump connected to said fourth node so that when a voltage is transferred from said second node to said fourth node, said second charge pump is turned on.

Claim 15

A memory cell circuit comprising: a volatile cell including first and second nodes having first and second stable states; a non-volatile cell including third and fourth nodes, a charge storage device for storing a charge representative of the state of said third and fourth nodes, and a terminal having a predetermined voltage when said charge storage device stores a charge representative of a predetermined one of the states of said third and fourth nodes; a transfer circuit for selectively transferring the state of said first and second nodes to said third and fourth nodes, and for selectively connecting a predetermined one of said volatile cell nodes to said terminal so that if said terminal is at said predetermined voltage said connected volatile cell node attains essentially the same voltage as said terminal; a first charge pump connected to said third node so that when a voltage is transferred from said first node to said third node, said first charge pump is turned on; and a second charge pump connected to said fourth node so that when a voltage is transferred from said second node to said fourth node, said second charge pump is turned on.

Claim 16

A memory cell circuit comprising: a volatile memory element comprising first and second output nodes and having two stable states; a non-volatile memory element comprising: third and fourth nodes selectively connectable to said first and second nodes; a first charge pump connected to said third node and to a first high voltage source, wherein said first charge pump is responsive to a voltage on said third node to apply substantially said high voltage to said third node; a second charge pump connected to aid fourth node and to a second high voltage source, wherein said second charge pump is responsive to a voltage on said fourth node to apply substantially said high voltage to said fourth node; charge storage device means connected to aid third and fourth nodes for storing a charge in response to a voltage difference between said thrid and fourth nodes; and a sensing device selectively connectable to said volatile memory element and responsive to said charge storage device to cause a predetermined voltage to be supplied to one of said volatile memory element nodes, but not to the other node, to cause said volatile element to assume a predetermined one of its states depending on the charge stored on said charge storage device.

Claim 17

A memory cell circuit comprising: a volatile memory element comprising first and second output nodes and having two stable states; a non-volatile memory element comprising: third and fourth nodes selectively connectable to said first and second nodes; a first charge pump connected to said third node and to a first high voltage source, wherein said first charge pump is responsive to a voltage on said third node to apply substantially said high voltage to said third node; a second charge pump connected to aid fourth node and to a second high voltage source, wherein said second charge pump is responsive to a voltage on said fourth node to apply substantially said high voltage to said fourth node; charge storage device means connected to aid third and fourth nodes for storing a charge in response to a voltage difference between said thrid and fourth nodes; and a sensing device selectively connectable to said volatile memory element and responsive to said charge storage device to cause a predetermined voltage to be supplied to one of said volatile memory element nodes, but not to the other node, to cause said volatile element to assume a predetermined one of its states depending on the charge stored on said charge storage device.

Claim 18

The memory cell circuit of claim 12 wherein : said first charge pump comprises: a first FET having a gate and a channel, and having its gate connected to said third node and its channel connected between said high voltage source and a first charge pump node; a second FET having a gate and a channel, and having its gate connected to said first charge pump node and its channel connected between said first charge pump node and said third memory node; and a third FET having a gate and a channel, and having its gate connected to said first charge pump node and another terminal connected to a clock line to capacitively couple said clock line to said first charge pump node; said second charge pump comprises: a fourth FET having a gate and a channel, and having its gate connected to said fourth node and its channel connected between said high voltage source and a second charge pump node; a fifth FET having a gate and a channel, and having its gate connected to said second charge pump node and its channel connected between said second charge pump node and said fourth memory node; and a sixth FET having a gate and a channel, and having its gate connected to said second charge pump node and another terminal connected to said clock line to capacitively couple said clock line to said second charge pump node.

Claim 19

The memory cell circuit of claim 13 wherein said first, second, fourth, and fifth FETs are natural MOSFETs requiring little voltage to render them conductive.

Claim 20

The memory cell circuit of claim 12, wherein said sensing device comprises: an output terminal that is coupled to a predetermined voltage source when said charge storage device is storing a first charge; and a transfer control circuit for selectively coupling one of said volatile element nodes to said output terminal.

Claim 21

The memory cell circuit of claim 12 wherein said first and second high voltage sources are the same.

Claim 24

The method of claim 17 wherein: said step of transferring the state of said volatile cell to said non-volatile cell comprises transferring the state of said volatile cell to a pair of nodes in said non-volatile cell; said step of storing a charge on said charge storage element comprises: activating a charge pump in response to a voltage on one of said non-volatile cell nodes to change the voltage of one of said nodes relative to the other; and applying said changed voltage across said charge storage element to store said charge representative of said state.

Claim 25

The method of claim 18, wherein said step of transferring the state of said volatile cell to said nodes in said non-volatile cell causes the voltage of said non-volatile cell nodes to rise, activating said charge pump.

Claim 26

The method of claim 17 wherein said step of sensing the charge on said charge storage element comprises: biasing a sensing element to either connect a terminal to a predetermined voltage or not depending on the charge stored in said charge storage element; and connecting said terminal to a node of said volatile element.