Abstract A self-aligned ion-implantation method for making a split-gate single transistor non-volatile electrically alterable semiconductor memory cell is disclosed. The method uses a silicon substrate. A layer of dielectric material is grown over the substrate. A layer of silicon is grown over the dielectric material. The silicon is masked to define a floating gate region. Ions then are implanted in the layer of silicon in the floating gate region to render the region conductive. Ions are then implanted through the floating gate region into the substrate to define the threshold in the substrate beneath the floating gate region. The floating gate region is then oxidized and patterned to form the floating gate. A second layer of dielectric material is deposited over the floating gate and over the substrate. A control gate is patterned and formed. The drain and the source regions in the substrate are defined.
A method of making a self-aligned electrically programmable and erasable memory device comprising the steps of: defining a substrate; growing a first layer of dielectric material over said substrate; depositing a layer of silicon over said first layer; masking said layer of silicon to define a floating gate region; implanting ions in said layer of silicon in said floating gate region to render said region conductive; implanting ions through said floating gate region into said substrate; patterning and forming a floating gate in the floating gate region; depositing a second layer of dielectric material over said floating gate and said substrate; patterning and forming a control gate; and defining a drain and a source region in said substrate.
Claim 2
Independent Claim
118 words
A method of making a self-aligned electrically programmable and erasable memory device comprising the steps of: defining a substrate; growing a first layer of dielectric material over said substrate; depositing a layer of silicon over said first layer; masking said layer of silicon to define a floating gate region; implanting ions in said layer of silicon in said floating gate region to render said region conductive; implanting ions through said floating gate region into said substrate; patterning and forming a floating gate in the floating gate region; depositing a second layer of dielectric material over said floating gate and said substrate; patterning and forming a control gate; and defining a drain and a source region in said substrate.
Claim 3
Dependent Claim
34 words
The method of claim 1 wherein said masking step further comprises: covering said layer of silicon with a protective material; and removing a portion of said protective material to define a floating gate region.
Claim 4
Dependent Claim
23 words
The method of claim 2 further comprises the step of: annealing said layer of silicon to form recrystallized silicon, after said covering step.
Claim 5
Dependent Claim
38 words
The method of claim 2 wherein the patterning step to form the floating gate comprises the steps of: growing masking oxide on said floating gate region; and removing the remainder of said protective material and the silicon thereunder.
Claim 6
Dependent Claim
15 words
The method of claim 1 wherein said second layer of dielectric material is silicon dioxide.
Claim 7
Dependent Claim
27 words
The method of claim 5 wherein said depositing said second layer step further comprises: performing nitridization of said silicon dioxide to form a layer of oxynitride film.
Claim 8
Dependent Claim
17 words
The method of claim 2 wherein said covering step further comprises: depositing a layer of silicon nitride.
Claim 9
Dependent Claim
46 words
The method of claim 7 wherein said removing a portion of said protective material further comprises: depositing a layer of photoresist: removing a portion of said photoresist to expose the protective material; and removing the protective material with the remainder of the photoresist as the mask.