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US4845047A Expired / Lapsed US ⏱️ 0.0 years remaining

Threshold adjustment method for an IGFET

Assignee: Texas Instruments Inc
•
Filing: 1987-06-25
•
Granted: 1989-07-04
•
Expires: 2007-06-25
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Abstract

Abstract Polysilicon gate insulated gate field effect transistors with threshold adjustment implants made after the gate oxide (156) and a split of the polysilicon gate (158) have been formed provides a shallow, tight dopant profile.

Inventors

  • 👤 Thomas C. Holloway
  • 👤 Roger A. Haken
  • 👤 Richard A. Chapman

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 04:36
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 52 words
A method of fabrication of insulated gate field effect transistors, comprising the steps of: (a) form a gate insulator on a semiconductor layer; (b) deposit gate electrode on said gate insulator; (c) implant threshold-adjustment dopants through both said gate insulator and said gate material; and then (d) form source and drain regions.
Claim 2
Independent Claim 52 words
A method of fabrication of insulated gate field effect transistors, comprising the steps of: (a) form a gate insulator on a semiconductor layer; (b) deposit gate electrode on said gate insulator; (c) implant threshold-adjustment dopants through both said gate insulator and said gate material; and then (d) form source and drain regions.
Claim 3
Dependent Claim 31 words
The method of claim 1, wherein: (a) said semiconductor layer is silicon; (b) said gate insulator is silicon dioxide; (c) said gate electrode is polysilicon; and (d) said dopant is boron.
Claim 4
Dependent Claim 25 words
The method of claim 1, wherein: (a) said semiconductor layer is silicon; (b) said gate electrode is refractory metal; and (c) said dopant is boron.
Claim 5
Independent Claim 102 words
The method of fabrication of integrated circuits, comprising the steps of: (a) forming gate insulator on regions of a semiconductor substrate; (b) depositing a first layer of conductive gate material on said gate insulator; (c) implanting threshold-adjustment dopants through both said conductive gate material and said gate insulator; (d) depositing a second layer of conductive gate material on said first layer; (e) patterning and etching field effect transistor gates in said layers of conductive gate material; (f) forming source and drain regions adjacent a plurality of said transistor gates; (g) forming source and drain contacts and interconnections; and (h) depositing passivation material.
Claim 6
Independent Claim 102 words
The method of fabrication of integrated circuits, comprising the steps of: (a) forming gate insulator on regions of a semiconductor substrate; (b) depositing a first layer of conductive gate material on said gate insulator; (c) implanting threshold-adjustment dopants through both said conductive gate material and said gate insulator; (d) depositing a second layer of conductive gate material on said first layer; (e) patterning and etching field effect transistor gates in said layers of conductive gate material; (f) forming source and drain regions adjacent a plurality of said transistor gates; (g) forming source and drain contacts and interconnections; and (h) depositing passivation material.
Claim 7
Dependent Claim 32 words
The method of claim 4, wherein; (a) said semiconductor layer is silicon; (b) said gate insulator is silicon dioxide; (c) said conductive gate material is polysilicon; and (d) said dopant is boron.
Claim 8
Dependent Claim 26 words
The method of claim 4, wherein; (a) said semiconductor layer is silicon; (b) said conductive gate material is refractory metal; and (c) said dopant is boron.

References Cited (Backward Citations)

JPS5687368A Cited
US4336647A Cited
JPS61198753A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-07-03 1993-01-02 1993-07-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-07-03 1997-01-02 1997-07-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-07-03 2001-01-02 2001-07-04 $7700.00 Window Closed / Lapsed

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